. Added SOP/EOP support to sim_transceiver_serializer and 
   sim_transceiver_deserializer.
-Instantiated tech_tse in eth_statistics.

names

Use p_dummy process to avoid reaching report failure when running tb for unb1 which has no 10gbase_r.

Added regression_test_vhdl key, with tb_tech_10gbase_r.vhd that is not self checking yet and not applicable to unb1.

Corrected hdl_library_clause_name = *_altera_emif_151 instead of 150, as declared in libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd

Added regression_test_vhdl key and test script modelsim_regression_test_vhdl.py that works ok for dp, diag and mac_10g libraries.

Use hdl_lib_include and unb*_board to include the 25M and 200M PLL IP for unb1 and the 125M and 200M PLL IP for unb2, unb2a

IP for dual rank DDR4 module (8GB) based on ~/altera_designs/ddr4_rev7 (MbI version, may also work on mbII)