Put IP for 10GbE MAC, PLL and base-R under hdl_lib_uses_ip.

libraries/technology/10gbase_r/hdllib.cfg

 hdl_lib_name = tech_10gbase_r
 hdl_library_clause_name = tech_10gbase_r_lib
-hdl_lib_uses_synth = technology
-                     tech_pll
-                     ip_arria10_phy_10gbase_r
-                     ip_arria10_phy_10gbase_r_4
-                     ip_arria10_phy_10gbase_r_12
-                     ip_arria10_phy_10gbase_r_24
-                     ip_arria10_phy_10gbase_r_48
-                     ip_arria10_transceiver_pll_10g
-                     ip_arria10_transceiver_reset_controller_1
-                     ip_arria10_transceiver_reset_controller_4
-                     ip_arria10_transceiver_reset_controller_12
-                     ip_arria10_transceiver_reset_controller_24
-                     ip_arria10_transceiver_reset_controller_48
-                     ip_arria10_e3sge3_phy_10gbase_r
-                     ip_arria10_e3sge3_phy_10gbase_r_4
-                     ip_arria10_e3sge3_phy_10gbase_r_12
-                     ip_arria10_e3sge3_phy_10gbase_r_24
-                     ip_arria10_e3sge3_phy_10gbase_r_48
-                     ip_arria10_e3sge3_transceiver_pll_10g
-                     ip_arria10_e3sge3_transceiver_reset_controller_1
-                     ip_arria10_e3sge3_transceiver_reset_controller_4
-                     ip_arria10_e3sge3_transceiver_reset_controller_12
-                     ip_arria10_e3sge3_transceiver_reset_controller_24
-                     ip_arria10_e3sge3_transceiver_reset_controller_48
-                     tech_transceiver
-                     common
+hdl_lib_uses_synth = technology common tech_pll tech_transceiver
+hdl_lib_uses_ip = ip_arria10_phy_10gbase_r                    ip_arria10_e3sge3_phy_10gbase_r                  
+                  ip_arria10_phy_10gbase_r_4                  ip_arria10_e3sge3_phy_10gbase_r_4                
+                  ip_arria10_phy_10gbase_r_12                 ip_arria10_e3sge3_phy_10gbase_r_12               
+                  ip_arria10_phy_10gbase_r_24                 ip_arria10_e3sge3_phy_10gbase_r_24               
+                  ip_arria10_phy_10gbase_r_48                 ip_arria10_e3sge3_phy_10gbase_r_48               
+                  ip_arria10_transceiver_pll_10g              ip_arria10_e3sge3_transceiver_pll_10g            
+                  ip_arria10_transceiver_reset_controller_1   ip_arria10_e3sge3_transceiver_reset_controller_1 
+                  ip_arria10_transceiver_reset_controller_4   ip_arria10_e3sge3_transceiver_reset_controller_4 
+                  ip_arria10_transceiver_reset_controller_12  ip_arria10_e3sge3_transceiver_reset_controller_12
+                  ip_arria10_transceiver_reset_controller_24  ip_arria10_e3sge3_transceiver_reset_controller_24
+                  ip_arria10_transceiver_reset_controller_48  ip_arria10_e3sge3_transceiver_reset_controller_48
+                     
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 

libraries/technology/mac_10g/hdllib.cfg

 hdl_lib_name = tech_mac_10g
 hdl_library_clause_name = tech_mac_10g_lib
-hdl_lib_uses_synth = technology ip_stratixiv_mac_10g ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g common dp
+hdl_lib_uses_synth = technology common dp ip_stratixiv_mac_10g
+hdl_lib_uses_ip = ip_arria10_mac_10g ip_arria10_e3sge3_mac_10g
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 

libraries/technology/pll/hdllib.cfg

 hdl_lib_name = tech_pll
 hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses_synth = technology common ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_uses_synth = technology common
 hdl_lib_uses_ip = ip_stratixiv_pll       ip_arria10_pll_clk200           ip_arria10_e3sge3_pll_clk200
                   ip_stratixiv_pll_clk25 ip_arria10_pll_clk25            ip_arria10_e3sge3_pll_clk25
                                          ip_arria10_pll_clk125           ip_arria10_e3sge3_pll_clk125
+                                         ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
 hdl_lib_uses_sim = 
 hdl_lib_technology =