added the fractional pll for clk125

libraries/technology/fractional_pll/hdllib.cfg

 hdl_lib_name = tech_fractional_pll
 hdl_library_clause_name = tech_fractional_pll_lib
-hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 common
+hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk125 common
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 
@@ -8,5 +8,6 @@ hdl_lib_technology =
 synth_files =
     tech_fractional_pll_component_pkg.vhd
     tech_fractional_pll_clk200.vhd
+    tech_fractional_pll_clk125.vhd
     
 test_bench_files =

libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_fractional_pll_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
+
+ENTITY tech_fractional_pll_clk125 IS
+  GENERIC (
+    g_technology       : NATURAL := c_tech_select_default
+  );
+  PORT (
+    areset  : IN STD_LOGIC  := '0';
+    inclk0  : IN STD_LOGIC  := '0';  -- 125 MHz
+    c0      : OUT STD_LOGIC ;        --  20 MHz
+    c1      : OUT STD_LOGIC ;        --  50 MHz
+    c2      : OUT STD_LOGIC ;        -- 100 MHz
+    c3      : OUT STD_LOGIC ;        -- 125 MHz
+    locked  : OUT STD_LOGIC 
+  );
+END tech_fractional_pll_clk125;
+
+ARCHITECTURE str OF tech_fractional_pll_clk125 IS
+
+BEGIN
+
+  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+    u0 : ip_arria10_fractional_pll_clk125
+    PORT MAP (
+  		outclk0       => c0,            --       outclk0.clk
+  		outclk1       => c1,            --       outclk1.clk
+  		outclk2       => c2,            --       outclk2.clk
+  		outclk3       => c3,            --       outclk3.clk
+  		pll_cal_busy  => OPEN,          --  pll_cal_busy.pll_cal_busy
+  		pll_locked    => locked,        --    pll_locked.pll_locked
+  		pll_powerdown => areset,        -- pll_powerdown.pll_powerdown
+  		pll_refclk0   => inclk0         --   pll_refclk0.clk
+    );
+  END GENERATE;
+
+END ARCHITECTURE;

libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd

@@ -43,6 +43,19 @@ PACKAGE tech_fractional_pll_component_pkg IS
   );
   END COMPONENT;
 
+  COMPONENT ip_arria10_fractional_pll_clk125 IS
+  PORT
+  (
+    outclk0       : out std_logic;        --       outclk0.clk
+    outclk1       : out std_logic;        --       outclk1.clk
+    outclk2       : out std_logic;        --       outclk2.clk
+    outclk3       : out std_logic;        --       outclk2.clk
+    pll_cal_busy  : out std_logic;        --  pll_cal_busy.pll_cal_busy
+    pll_locked    : out std_logic;        --    pll_locked.pll_locked
+    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
+    pll_refclk0   : in  std_logic := '0'  --   pll_refclk0.clk
+  );
+  END COMPONENT;
   
 END tech_fractional_pll_component_pkg;
 

libraries/technology/pll/tech_pll_component_pkg.vhd

@@ -161,6 +161,19 @@ PACKAGE tech_pll_component_pkg IS
     locked    : OUT STD_LOGIC 
   );
   END COMPONENT;
+
+--  COMPONENT ip_arria10_pll_clk200mm IS
+--  PORT
+--  (
+--    rst       : IN STD_LOGIC  := '0';
+--    refclk    : IN STD_LOGIC  := '0';
+--    outclk_0  : OUT STD_LOGIC ;
+--    outclk_1  : OUT STD_LOGIC ;
+--    outclk_2  : OUT STD_LOGIC ;
+--    outclk_3  : OUT STD_LOGIC ;
+--    locked    : OUT STD_LOGIC 
+--  );
+--  END COMPONENT;
   
 END tech_pll_component_pkg;