Added tech_pll_xgmii_mac_clocks.vhd

libraries/technology/pll/hdllib.cfg

 hdl_lib_name = tech_pll
 hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses = technology ip_stratixiv_pll
+hdl_lib_uses = technology ip_stratixiv_pll ip_arria10_pll_xgmii_mac_clocks common
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR
@@ -10,5 +10,6 @@ synth_files =
     tech_pll_component_pkg.vhd
     tech_pll_clk200.vhd
     tech_pll_clk200_p6.vhd
+    tech_pll_xgmii_mac_clocks.vhd
     
 test_bench_files =

libraries/technology/pll/tech_pll_component_pkg.vhd

@@ -26,6 +26,11 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 PACKAGE tech_pll_component_pkg IS
 
+  CONSTANT tech_pll_clk_644_period      : TIME := 1551520 fs;                       -- = 1.551520 ns ~= 644.53125 MHz
+  CONSTANT tech_pll_clk_156_period      : TIME := (tech_pll_clk_644_period*33)/8;   -- = 6.400020 ns ~= 156.25 MHz
+  CONSTANT tech_pll_clk_312_period      : TIME := (tech_pll_clk_644_period*33)/16;  -- = 3.200010 ns ~= 312.5 MHz
+
+
   -----------------------------------------------------------------------------
   -- ip_stratixiv
   -----------------------------------------------------------------------------
@@ -36,15 +41,15 @@ PACKAGE tech_pll_component_pkg IS
     g_clk0_phase_shift : STRING := "0";
     g_clk1_phase_shift : STRING := "0"
   );
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
+  PORT
+  (
+    areset    : IN STD_LOGIC  := '0';
+    inclk0    : IN STD_LOGIC  := '0';
+    c0    : OUT STD_LOGIC ;
+    c1    : OUT STD_LOGIC ;
+    c2    : OUT STD_LOGIC ;
+    locked    : OUT STD_LOGIC 
+  );
   END COMPONENT;
   
   COMPONENT ip_stratixiv_pll_clk200_p6 IS
@@ -73,19 +78,19 @@ PACKAGE tech_pll_component_pkg IS
     g_clk6_phase_shift : STRING := "938"         -- = 067.5 
                                 -- "1094"        -- = 078.75
   );
-	PORT
-	(
-		areset		: IN STD_LOGIC  := '0';
-		inclk0		: IN STD_LOGIC  := '0';
-		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC ;
-		c4		: OUT STD_LOGIC ;
-		c5		: OUT STD_LOGIC ;
-		c6		: OUT STD_LOGIC ;
-		locked		: OUT STD_LOGIC 
-	);
+  PORT
+  (
+    areset    : IN STD_LOGIC  := '0';
+    inclk0    : IN STD_LOGIC  := '0';
+    c0    : OUT STD_LOGIC ;
+    c1    : OUT STD_LOGIC ;
+    c2    : OUT STD_LOGIC ;
+    c3    : OUT STD_LOGIC ;
+    c4    : OUT STD_LOGIC ;
+    c5    : OUT STD_LOGIC ;
+    c6    : OUT STD_LOGIC ;
+    locked    : OUT STD_LOGIC 
+  );
   END COMPONENT;
   
   
@@ -93,5 +98,15 @@ PACKAGE tech_pll_component_pkg IS
   -- ip_arria10
   -----------------------------------------------------------------------------
   
+  COMPONENT ip_arria10_pll_xgmii_mac_clocks IS
+  PORT (
+    pll_refclk0   : in  std_logic := '0'; --   pll_refclk0.clk
+    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
+    pll_locked    : out std_logic;        --    pll_locked.pll_locked
+    outclk0       : out std_logic;        --       outclk0.clk
+    pll_cal_busy  : out std_logic;        --  pll_cal_busy.pll_cal_busy
+    outclk1       : out std_logic         --       outclk1.clk
+  );
+  END COMPONENT;
   
 END tech_pll_component_pkg;

libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Create 156.25 and 312.5  MHz clocks for 10GBASE-R and MAC-10G
+-- Description:
+--   The reference clock frequency for the PLL is 644.53125 MHz.
+-- Remark:
+-- . This PLL is typically instantiated at the top level of a design in the
+--   board support component rather than at the ETH-10G instance. The
+--   advantages are:
+--   - this avoids having to propagate up the PLL output clocks through the
+--     hierarchy, which can cause delta-cycle mismatch between clock
+--     processes at different levels in the hierarchy.
+--   - the 156 and 312 MHz clocks are also available for other purposes.
+-- . 
+
+LIBRARY ieee, technology_lib, common_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_pll_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_140;
+
+ENTITY tech_pll_xgmii_mac_clocks IS
+  GENERIC (
+    g_technology  : NATURAL := c_tech_select_default
+  );
+  PORT (
+    refclk_644 : IN  STD_LOGIC;   -- 644.53125 MHz reference clock for PLL
+    clk_156    : OUT STD_LOGIC;   -- 156.25 MHz PLL output clock
+    clk_312    : OUT STD_LOGIC;   -- 312.5  MHz PLL output clock
+    rst_156    : OUT STD_LOGIC;   -- reset in clk_156 domain based on PLL locked
+    rst_312    : OUT STD_LOGIC    -- reset in clk_312 domain based on PLL locked
+  );
+END tech_pll_xgmii_mac_clocks;
+
+ARCHITECTURE str OF tech_pll_xgmii_mac_clocks IS
+
+  SIGNAL pll_locked    : STD_LOGIC;
+  SIGNAL pll_locked_n  : STD_LOGIC;
+  
+  SIGNAL i_clk_156     : STD_LOGIC;
+  SIGNAL i_clk_312     : STD_LOGIC;
+  
+BEGIN
+
+  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+    u0 : ip_arria10_pll_xgmii_mac_clocks
+    PORT MAP (
+      pll_refclk0   => refclk_644,
+      pll_powerdown => '0',
+      pll_locked    => pll_locked,
+      outclk0       => i_clk_156,
+      pll_cal_busy  => OPEN,
+      outclk1       => i_clk_312
+    );
+  END GENERATE;
+  
+  pll_locked_n <= NOT pll_locked;
+  
+  -- The delta-cycle difference in simulation between i_clk and output clk is no issue because i_clk is only used to create rst which is not clk cycle critical
+  clk_156 <= i_clk_156;
+  clk_312 <= i_clk_312;
+  
+  u_common_areset_156 : ENTITY common_lib.common_areset
+  GENERIC MAP (
+    g_rst_level => '1',
+    g_delay_len => c_meta_delay_len
+  )
+  PORT MAP (
+    in_rst    => pll_locked_n,
+    clk       => i_clk_156,
+    out_rst   => rst_156
+  );
+  
+  u_common_areset_312 : ENTITY common_lib.common_areset
+  GENERIC MAP (
+    g_rst_level => '1',
+    g_delay_len => c_meta_delay_len
+  )
+  PORT MAP (
+    in_rst    => pll_locked_n,
+    clk       => i_clk_312,
+    out_rst   => rst_312
+  );
+  
+END ARCHITECTURE;