added components for ip_arria10_e3sge3

libraries/technology/clkbuf/tech_clkbuf.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_clkbuf_global_altclkctrl_150;
+LIBRARY ip_arria10_e3sge3_clkbuf_global_altclkctrl_151;
 
 ENTITY tech_clkbuf IS
   GENERIC (
@@ -55,4 +56,15 @@ BEGIN
     );
   END GENERATE;
 
+  -----------------------------------------------------------------------------
+  -- ip_arria10_e3sge3
+  -----------------------------------------------------------------------------
+  
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 AND g_clock_net="GLOBAL" GENERATE
+    u0 : ip_arria10_e3sge3_clkbuf_global
+    PORT MAP (
+      inclk  => inclk,   -- inclk
+      outclk => outclk   -- outclk
+    );
+  END GENERATE;
 END ARCHITECTURE;

libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd

@@ -37,5 +37,17 @@ PACKAGE tech_clkbuf_component_pkg IS
   );
   END COMPONENT;
 
+
+  -----------------------------------------------------------------------------
+  -- ip_arria10_e3sge3
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_arria10_e3sge3_clkbuf_global IS
+  PORT (
+    inclk  : in  std_logic := '0'; --  altclkctrl_input.inclk
+    outclk : out std_logic         -- altclkctrl_output.outclk
+  );
+  END COMPONENT;
+    
 END tech_clkbuf_component_pkg;
 

libraries/technology/fifo/hdllib.cfg

 hdl_lib_name = tech_fifo
 hdl_library_clause_name = tech_fifo_lib
-hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo
+hdl_lib_uses_synth = technology ip_stratixiv_fifo ip_arria10_fifo ip_arria10_e3sge3_fifo
 hdl_lib_uses_sim = 
 
 hdl_lib_technology = 

libraries/technology/fifo/tech_fifo_component_pkg.vhd

@@ -93,7 +93,7 @@ PACKAGE tech_fifo_component_pkg IS
   
   
   -----------------------------------------------------------------------------
-  -- ip_stratixiv
+  -- ip_arria10
   -----------------------------------------------------------------------------
   
   COMPONENT ip_arria10_fifo_sc IS
@@ -157,4 +157,70 @@ PACKAGE tech_fifo_component_pkg IS
   );
   END COMPONENT;
 
+  -----------------------------------------------------------------------------
+  -- ip_arria10_e3sge3
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_arria10_e3sge3_fifo_sc IS
+  GENERIC (
+    g_use_eab   : STRING := "ON";
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC ;
+    clock   : IN STD_LOGIC ;
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdreq   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    empty   : OUT STD_LOGIC ;
+    full    : OUT STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+    usedw   : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+  COMPONENT ip_arria10_e3sge3_fifo_dc IS
+  GENERIC (
+    g_use_eab   : STRING := "ON";
+    g_dat_w     : NATURAL := 20;
+    g_nof_words : NATURAL := 1024
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT ip_arria10_e3sge3_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_nof_words : NATURAL := 1024;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : NATURAL := 20;
+    g_rddat_w   : NATURAL := 10
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC ;
+    rdreq   : IN STD_LOGIC ;
+    wrclk   : IN STD_LOGIC ;
+    wrreq   : IN STD_LOGIC ;
+    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC ;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC ;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  
 END tech_fifo_component_pkg;

libraries/technology/fifo/tech_fifo_dc.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
+LIBRARY ip_arria10_e3sge3_fifo_lib;
 
 ENTITY tech_fifo_dc IS
   GENERIC (
@@ -68,4 +69,10 @@ BEGIN
     PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_fifo_dc
+    GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
+LIBRARY ip_arria10_e3sge3_fifo_lib;
 
 ENTITY tech_fifo_dc_mixed_widths IS
   GENERIC (
@@ -68,4 +69,10 @@ BEGIN
     PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_fifo_dc_mixed_widths
+    GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/fifo/tech_fifo_sc.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_fifo_lib;
 LIBRARY ip_arria10_fifo_lib;
+LIBRARY ip_arria10_e3sge3_fifo_lib;
 
 ENTITY tech_fifo_sc IS
   GENERIC (
@@ -66,4 +67,10 @@ BEGIN
     PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_fifo_sc
+    GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+    PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/flash/tech_flash_asmi_parallel.vhd

@@ -30,6 +30,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_asmi_parallel_altera_asmi_parallel_150;
+LIBRARY ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151;
 
 ENTITY tech_flash_asmi_parallel IS
   GENERIC (
@@ -77,4 +78,9 @@ BEGIN
     PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_asmi_parallel
+    PORT MAP (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
+  END GENERATE;
+   
 END ARCHITECTURE;

libraries/technology/flash/tech_flash_component_pkg.vhd

@@ -112,6 +112,51 @@ PACKAGE tech_flash_component_pkg IS
   );
   end component ip_arria10_remote_update;
 
+
+  -----------------------------------------------------------------------------
+  -- ip_arria10_e3sge3
+  -----------------------------------------------------------------------------
+
+  component ip_arria10_e3sge3_asmi_parallel is
+  port (
+    addr          : in  std_logic_vector(31 downto 0);
+    clkin         : in  std_logic;
+    datain        : in  std_logic_vector(7 downto 0); 
+    rden          : in  std_logic;
+    read          : in  std_logic;
+    sector_erase  : in  std_logic;
+    shift_bytes   : in  std_logic;
+    wren          : in  std_logic;
+    write         : in  std_logic;
+    busy          : out std_logic;
+    data_valid    : out std_logic;
+    dataout       : out std_logic_vector(7 downto 0);
+    illegal_erase : out std_logic;
+    illegal_write : out std_logic;
+    reset         : in  std_logic; 
+    sce           : in  std_logic_vector(2 downto 0);
+    en4b_addr     : in  std_logic
+  );
+  end component ip_arria10_e3sge3_asmi_parallel;
+
+  -- note the EPCQ-L1024 device appears not to be supported yet.
+  -- the EPCA-512 was chosen instead
+
+  component ip_arria10_e3sge3_remote_update is
+  port (
+    clock       : in  std_logic;
+    data_in     : in  std_logic_vector(31 downto 0);
+    param       : in  std_logic_vector(2 downto 0);
+    read_param  : in  std_logic;
+    reconfig    : in  std_logic;
+    reset       : in  std_logic; 
+    reset_timer : in  std_logic; 
+    write_param : in  std_logic; 
+    busy        : out std_logic; 
+    data_out    : out std_logic_vector(31 downto 0)
+  );
+  end component ip_arria10_e3sge3_remote_update;
+
   function tech_flash_addr_w( technology: in integer ) return integer;
   function tech_flash_data_w( technology: in integer ) return integer;
 
@@ -127,6 +172,9 @@ package body tech_flash_component_pkg is
     if technology = c_tech_arria10 then
         return 32;
     end if;		  
+    if technology = c_tech_arria10_e3sge3 then
+        return 32;
+    end if;		  
   end;
 
   function tech_flash_data_w( technology : in integer )  return integer is 
@@ -137,6 +185,9 @@ package body tech_flash_component_pkg is
     if technology = c_tech_arria10 then
         return 32;
     end if;		  
+    if technology = c_tech_arria10_e3sge3 then
+        return 32;
+    end if;		  
   end;
 
 

libraries/technology/flash/tech_flash_remote_update.vhd

@@ -30,6 +30,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_flash_lib;
 LIBRARY ip_arria10_remote_update_altera_remote_update_150;
+LIBRARY ip_arria10_e3sge3_remote_update_altera_remote_update_151;
 
 ENTITY tech_flash_remote_update IS
   GENERIC (
@@ -66,4 +67,9 @@ BEGIN
     u0 : ip_arria10_remote_update
     PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
   END GENERATE;
+
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_remote_update
+    PORT MAP (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
+  END GENERATE;
 END ARCHITECTURE;

libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_temp_sense_altera_temp_sense_150;
+LIBRARY ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
 
 
 ENTITY tech_fpga_temp_sens IS

libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd

@@ -35,5 +35,14 @@ PACKAGE tech_fpga_temp_sens_component_pkg IS
   	);
   END COMPONENT;
 
+  COMPONENT ip_arria10_e3sge3_temp_sense IS
+  	PORT (
+  		corectl : IN  STD_LOGIC := '0';            -- corectl.corectl
+  		eoc     : OUT STD_LOGIC;                   -- eoc.eoc
+  		reset   : IN  STD_LOGIC := '0';            -- reset.reset
+  		tempout : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) -- tempout.tempout
+  	);
+  END COMPONENT;
+
 END tech_fpga_temp_sens_component_pkg;
 

libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
 
 LIBRARY ip_arria10_voltage_sense_altera_voltage_sense_150;
+LIBRARY ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
 
 
 ENTITY tech_fpga_voltage_sens IS

libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd

@@ -44,5 +44,23 @@ PACKAGE tech_fpga_voltage_sens_component_pkg IS
   	);
   END COMPONENT;
 
+  COMPONENT ip_arria10_e3sge3_voltage_sense IS
+  	PORT (
+  		clock_clk                    : in  STD_LOGIC := '0';            
+  		reset_sink_reset             : in  STD_LOGIC;                   
+  		controller_csr_address       : in  STD_LOGIC := '0';           
+  		controller_csr_read          : in  STD_LOGIC := '0';           
+  		controller_csr_write         : in  STD_LOGIC := '0';           
+  		controller_csr_writedata     : in  STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
+  		controller_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
+  		sample_store_csr_address     : in  STD_LOGIC_VECTOR(3 downto 0) := "0000";           
+  		sample_store_csr_read        : in  STD_LOGIC := '0';           
+  		sample_store_csr_write       : in  STD_LOGIC := '0';           
+  		sample_store_csr_writedata   : in  STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
+  		sample_store_csr_readdata      : out STD_LOGIC_VECTOR(31 downto 0) := (others => '0');     
+  		sample_store_irq_irq         : out STD_LOGIC
+  	);
+  END COMPONENT;
+
 END tech_fpga_voltage_sens_component_pkg;
 

libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk125_altera_xcvr_fpll_a10_150;
+LIBRARY ip_arria10_e3sge3_fractional_pll_clk125_altera_xcvr_fpll_a10_151;
 
 ENTITY tech_fractional_pll_clk125 IS
   GENERIC (

libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd

@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_fractional_pll_clk200_altera_xcvr_fpll_a10_150;
+LIBRARY ip_arria10_e3sge3_fractional_pll_clk200_altera_xcvr_fpll_a10_151;
 
 ENTITY tech_fractional_pll_clk200 IS
   GENERIC (

libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd

@@ -57,5 +57,36 @@ PACKAGE tech_fractional_pll_component_pkg IS
   );
   END COMPONENT;
 
+  -----------------------------------------------------------------------------
+  -- ip_arria10_e3sge3
+  -----------------------------------------------------------------------------
+    
+  COMPONENT ip_arria10_e3sge3_fractional_pll_clk200 IS
+  PORT
+  (
+    outclk0       : out std_logic;        --       outclk0.clk
+    outclk1       : out std_logic;        --       outclk1.clk
+    outclk2       : out std_logic;        --       outclk2.clk
+    pll_cal_busy  : out std_logic;        --  pll_cal_busy.pll_cal_busy
+    pll_locked    : out std_logic;        --    pll_locked.pll_locked
+    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
+    pll_refclk0   : in  std_logic := '0'  --   pll_refclk0.clk
+  );
+  END COMPONENT;
+
+  COMPONENT ip_arria10_e3sge3_fractional_pll_clk125 IS
+  PORT
+  (
+    outclk0       : out std_logic;        --       outclk0.clk
+    outclk1       : out std_logic;        --       outclk1.clk
+    outclk2       : out std_logic;        --       outclk2.clk
+    outclk3       : out std_logic;        --       outclk2.clk
+    pll_cal_busy  : out std_logic;        --  pll_cal_busy.pll_cal_busy
+    pll_locked    : out std_logic;        --    pll_locked.pll_locked
+    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
+    pll_refclk0   : in  std_logic := '0'  --   pll_refclk0.clk
+  );
+  END COMPONENT;
+  
 END tech_fractional_pll_component_pkg;
 

libraries/technology/iobuf/tech_iobuf_component_pkg.vhd

@@ -93,4 +93,36 @@ PACKAGE tech_iobuf_component_pkg IS
   );
   END COMPONENT;
   
+  -----------------------------------------------------------------------------
+  -- ip_arria10_e3sge3
+  -----------------------------------------------------------------------------
+  
+  COMPONENT ip_arria10_e3sge3_ddio_in IS
+  GENERIC (
+    g_width : NATURAL := 1
+  );
+  PORT (
+    in_dat      : IN  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_clk      : IN  STD_LOGIC;
+    in_clk_en   : IN  STD_LOGIC := '1';   -- Not Connected
+    rst         : IN  STD_LOGIC := '0';
+    out_dat_hi  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat_lo  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT ip_arria10_e3sge3_ddio_out IS
+  GENERIC(
+    g_width : NATURAL := 1
+  );
+  PORT (
+    rst        : IN   STD_LOGIC := '0';
+    in_clk     : IN   STD_LOGIC;
+    in_clk_en  : IN   STD_LOGIC := '1';   -- Not Connected
+    in_dat_hi  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_dat_lo  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat    : OUT  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
 END tech_iobuf_component_pkg;

libraries/technology/iobuf/tech_iobuf_ddio_in.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_ddio_lib;
 LIBRARY ip_arria10_ddio_lib;
+LIBRARY ip_arria10_e3sge3_ddio_lib;
 
 ENTITY tech_iobuf_ddio_in IS
   GENERIC (
@@ -61,4 +62,10 @@ BEGIN
     PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_ddio_in
+    GENERIC MAP (g_width)
+    PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
+  END GENERATE;
+  
 END ARCHITECTURE;

libraries/technology/iobuf/tech_iobuf_ddio_out.vhd

@@ -28,6 +28,7 @@ USE technology_lib.technology_select_pkg.ALL;
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_stratixiv_ddio_lib;
 LIBRARY ip_arria10_ddio_lib;
+LIBRARY ip_arria10_e3sge3_ddio_lib;
 
 ENTITY tech_iobuf_ddio_out IS
   GENERIC (
@@ -61,4 +62,10 @@ BEGIN
     PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
   END GENERATE;
 
+  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
+    u0 : ip_arria10_e3sge3_ddio_out
+    GENERIC MAP (g_width)
+    PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
+  END GENERATE;
+  
 END ARCHITECTURE;