Added tech_pll_clk_644_10ppm for 10 ppm offset to 644.53125 MHz period.

libraries/technology/pll/tech_pll_component_pkg.vhd

@@ -26,10 +26,13 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 PACKAGE tech_pll_component_pkg IS
 
+  -- Choose multiple of 16 fs to avoid truncation by simulator
   CONSTANT tech_pll_clk_644_period      : TIME := 1551520 fs;                       -- = 1.551520 ns ~= 644.53125 MHz
   CONSTANT tech_pll_clk_156_period      : TIME := (tech_pll_clk_644_period*33)/8;   -- = 6.400020 ns ~= 156.25 MHz
   CONSTANT tech_pll_clk_312_period      : TIME := (tech_pll_clk_644_period*33)/16;  -- = 3.200010 ns ~= 312.5 MHz
 
+  -- Reference clock offset: +100 ppm ~= 155 fs ~= 9*16 = 144 fs
+  CONSTANT tech_pll_clk_644_10ppm       : TIME := 16 fs;
 
   -----------------------------------------------------------------------------
   -- ip_stratixiv