added PLL for stratix. This PLL has 25MHz input and 4 outputs; purpose

libraries/technology/ip_stratixiv/pll_clk25/hdllib.cfg

...hnology/ip_stratixiv/pll_clk25/ip_stratixiv_pll_clk25.vhd

libraries/technology/pll/hdllib.cfg

libraries/technology/pll/tech_pll_clk25.vhd

libraries/technology/pll/tech_pll_component_pkg.vhd