Removed clock domain crossing logic for this control register, because that is done by io_ddr_cross_domain.vhd in io_ddr.vhd. Removed cal_fail and cal_ok, because these are already available via the io_ddr status register.

 . 3 identical firmware image with different default RAM contents:
 . Used on FN0,FN1,FN2 to validate apertif_unb1_correlator.

 . Validated with apertif_unb1_fn_bf_emu running on 3 FNs.

 window navigation in simulation.

-Using new HEX filenames;
-In the TB, connected RX so 10GbE TX enables XON.

 pre-BSN aligner stage;
-Set g_remove_crc in dp_offload_rx to FALSE;
-Verified in sim and validated on hardware: OK using locally modded filter
 in WPFB with gap support.