-Added HEX files voor 3 front nodes;

-Using new HEX filenames;
-In the TB, connected RX so 10GbE TX enables XON.

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn0_0.hex

+:02000000007589
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+:02007E0000750B
+:02007F00067405
+:00000001FF

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn0_1.hex

+:020000000C747E
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+:02007F001273FA
+:00000001FF

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn0_2.hex

+:02000000187274
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+:00000001FF

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn0_3.hex

+:02000000246F6B
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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn1_0.hex

+:02000000027488
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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn1_1.hex

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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn1_2.hex

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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn1_3.hex

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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn2_0.hex

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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn2_1.hex

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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn2_2.hex

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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/hex/bg_data_fn2_3.hex

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applications/apertif/designs/apertif_unb1_fn_bf_emu/src/python/gen_hex_files_block_gen.py

@@ -66,7 +66,7 @@ x = np.linspace(0.0, N*T, N)
 AMPL_MAX = 127
 CHANNELS = [1,5,12,17,21,25,28,34,41,47,54,55,60]
 NOF_CHANNELS = len(CHANNELS)
-
+input_signals_concat_inter
 input_signals = []
 for input_signal_nr in range(NOF_INPUT_SIGNALS):
     phase_shift_deg = input_signal_nr

applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd

@@ -23,6 +23,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
 USE common_lib.common_field_pkg.ALL;
 USE common_lib.common_network_layers_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
@@ -206,10 +207,10 @@ BEGIN
     g_nof_streams        => 4,
     g_buf_dat_w          => 16,
     g_buf_addr_w         => ceil_log2(2*64),
-    g_file_name_prefix   => "hex/bg_data",
-    g_diag_block_gen_rst => c_bg_ctrl
-  )
-  PORT MAP (
+    g_file_name_prefix   => "hex/bg_data_fn" & int_to_str(g_sim_node_nr), -- In simulation: FN0: bg_data_fn0_0..3
+    g_diag_block_gen_rst => c_bg_ctrl      --                                   FN1: bg_data_fn1_0..3
+  )                                        --                                   FN2: bg_data_fn2_0..1
+  PORT MAP (                               --                    In hardware:   FN0,FN1,FN2: bg_data_fn#_0..3 files are renamed after synth, MIF update, assembler re-run. Same results. 
     mm_rst           => mm_rst,
     mm_clk           => mm_clk,
   
@@ -268,7 +269,7 @@ BEGIN
   u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
   GENERIC MAP(
     g_sim             => g_sim,
-    g_sim_level       => 0,
+    g_sim_level       => 1,
     g_nof_macs        => c_nof_10GbE_offload_streams,
     g_use_mdio        => TRUE,
     g_tx_fifo_fill    => c_pkt_len, 
@@ -421,6 +422,7 @@ BEGIN
   u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
   GENERIC MAP (
     g_sim                     => g_sim,
+    g_sim_flash_model         => FALSE,
     g_design_name             => g_design_name,
     g_design_note             => g_design_note,
     g_stamp_date              => g_stamp_date,