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RTSD
HDL
Commits
aee49add
Commit
aee49add
authored
9 years ago
by
Daniel van der Schuur
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-Connected RX serial links.
parent
8d58e164
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applications/apertif/systems/apertif_bg_xc/tb/vhdl/tb_apertif_bg_xc.vhd
+36
-28
36 additions, 28 deletions
...pertif/systems/apertif_bg_xc/tb/vhdl/tb_apertif_bg_xc.vhd
with
36 additions
and
28 deletions
applications/apertif/systems/apertif_bg_xc/tb/vhdl/tb_apertif_bg_xc.vhd
+
36
−
28
View file @
aee49add
...
@@ -59,8 +59,10 @@ ARCHITECTURE tb OF tb_apertif_bg_xc IS
...
@@ -59,8 +59,10 @@ ARCHITECTURE tb OF tb_apertif_bg_xc IS
SIGNAL
ID
:
STD_LOGIC_VECTOR
(
c_unb1_board_aux
.
id_w
-1
DOWNTO
0
)
:
=
c_id
;
SIGNAL
ID
:
STD_LOGIC_VECTOR
(
c_unb1_board_aux
.
id_w
-1
DOWNTO
0
)
:
=
c_id
;
SIGNAL
si_fn_0_tx
:
STD_LOGIC_VECTOR
(
c_unb1_board_ci
.
tr
.
bus_w
-1
DOWNTO
0
)
:
=
(
OTHERS
=>
'0'
);
TYPE
t_emu_si_fn_0_tr_arr
IS
ARRAY
(
2
DOWNTO
0
)
OF
STD_LOGIC_VECTOR
(
c_unb1_board_ci
.
tr
.
bus_w
-1
DOWNTO
0
);
SIGNAL
emu_si_fn_0_tx_arr
:
t_emu_si_fn_0_tr_arr
;
SIGNAL
emu_si_fn_0_rx_arr
:
t_emu_si_fn_0_tr_arr
;
BEGIN
BEGIN
----------------------------------------------------------------------------
----------------------------------------------------------------------------
...
@@ -74,30 +76,32 @@ BEGIN
...
@@ -74,30 +76,32 @@ BEGIN
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- 3x apertif_unb1_fn_bf_emu
-- 3x apertif_unb1_fn_bf_emu
------------------------------------------------------------------------------
------------------------------------------------------------------------------
u_apertif_unb1_fn_bf_emu
:
ENTITY
apertif_unb1_fn_bf_emu_lib
.
apertif_unb1_fn_bf_emu
gen_apertif_unb1_fn_bf_emu
:
FOR
i
IN
0
TO
2
GENERATE
GENERIC
MAP
(
u_apertif_unb1_fn_bf_emu
:
ENTITY
apertif_unb1_fn_bf_emu_lib
.
apertif_unb1_fn_bf_emu
g_sim
=>
c_sim
,
GENERIC
MAP
(
g_sim_unb_nr
=>
c_unb_nr
,
g_sim
=>
c_sim
,
g_sim_node_nr
=>
c_node_nr
g_sim_unb_nr
=>
c_unb_nr
,
)
g_sim_node_nr
=>
i
PORT
MAP
(
)
CLK
=>
clk
,
PORT
MAP
(
PPS
=>
pps
,
CLK
=>
clk
,
VERSION
=>
"00"
,
PPS
=>
pps
,
ID
=>
ID
,
VERSION
=>
"00"
,
ID
=>
ID
,
ETH_clk
=>
eth_clk
,
ETH_SGIN
=>
'0'
,
SA_CLK
=>
tr_clk
,
SI_FN_0_RX
=>
(
OTHERS
=>
'0'
),
ETH_clk
=>
eth_clk
,
SI_FN_1_RX
=>
(
OTHERS
=>
'0'
),
ETH_SGIN
=>
'0'
,
SI_FN_2_RX
=>
(
OTHERS
=>
'0'
),
SI_FN_3_RX
=>
(
OTHERS
=>
'0'
),
SA_CLK
=>
tr_clk
,
SI_FN_0_TX
=>
si_fn_0_tx
SI_FN_0_TX
=>
emu_si_fn_0_tx_arr
(
i
),
);
SI_FN_0_RX
=>
emu_si_fn_0_rx_arr
(
i
),
-- Only connected for OK link status check in emu 10GbE TX
SI_FN_1_RX
=>
(
OTHERS
=>
'0'
),
SI_FN_2_RX
=>
(
OTHERS
=>
'0'
),
SI_FN_3_RX
=>
(
OTHERS
=>
'0'
)
);
END
GENERATE
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- apertif_unb1_correlator
-- apertif_unb1_correlator
...
@@ -121,9 +125,13 @@ BEGIN
...
@@ -121,9 +125,13 @@ BEGIN
SA_CLK
=>
tr_clk
,
SA_CLK
=>
tr_clk
,
SB_CLK
=>
tr_clk
,
SB_CLK
=>
tr_clk
,
SI_FN_0_RX
=>
si_fn_0_tx
,
SI_FN_0_RX
=>
emu_si_fn_0_tx_arr
(
0
),
SI_FN_1_RX
=>
si_fn_0_tx
,
SI_FN_0_TX
=>
emu_si_fn_0_rx_arr
(
0
),
SI_FN_2_RX
=>
si_fn_0_tx
,
SI_FN_1_RX
=>
emu_si_fn_0_tx_arr
(
1
),
SI_FN_1_TX
=>
emu_si_fn_0_rx_arr
(
1
),
SI_FN_2_RX
=>
emu_si_fn_0_tx_arr
(
2
),
SI_FN_2_TX
=>
emu_si_fn_0_rx_arr
(
2
),
SI_FN_3_RX
=>
(
OTHERS
=>
'0'
),
SI_FN_3_RX
=>
(
OTHERS
=>
'0'
),
FN_BN_0_RX
=>
(
OTHERS
=>
'0'
),
FN_BN_0_RX
=>
(
OTHERS
=>
'0'
),
...
...
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