-Connected RX serial links.

applications/apertif/systems/apertif_bg_xc/tb/vhdl/tb_apertif_bg_xc.vhd

@@ -59,7 +59,9 @@ ARCHITECTURE tb OF tb_apertif_bg_xc IS
   
   SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id;
 
-  SIGNAL si_fn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
+  TYPE t_emu_si_fn_0_tr_arr IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);  
+  SIGNAL emu_si_fn_0_tx_arr  : t_emu_si_fn_0_tr_arr;
+  SIGNAL emu_si_fn_0_rx_arr  : t_emu_si_fn_0_tr_arr;
 
 BEGIN
 
@@ -74,11 +76,12 @@ BEGIN
   ------------------------------------------------------------------------------
   -- 3x apertif_unb1_fn_bf_emu
   ------------------------------------------------------------------------------
+  gen_apertif_unb1_fn_bf_emu : FOR i IN 0 TO 2 GENERATE
     u_apertif_unb1_fn_bf_emu : ENTITY apertif_unb1_fn_bf_emu_lib.apertif_unb1_fn_bf_emu
       GENERIC MAP (
         g_sim         => c_sim,
         g_sim_unb_nr  => c_unb_nr,
-      g_sim_node_nr => c_node_nr
+        g_sim_node_nr => i
       )
       PORT MAP (
         CLK         => clk,
@@ -91,13 +94,14 @@ BEGIN
         
         SA_CLK      => tr_clk,
     
-      SI_FN_0_RX  => (OTHERS=>'0'),
+        SI_FN_0_TX  => emu_si_fn_0_tx_arr(i),
+        SI_FN_0_RX  => emu_si_fn_0_rx_arr(i), -- Only connected for OK link status check in emu 10GbE TX
+
         SI_FN_1_RX  => (OTHERS=>'0'),
         SI_FN_2_RX  => (OTHERS=>'0'),
-      SI_FN_3_RX  => (OTHERS=>'0'),
-
-      SI_FN_0_TX  => si_fn_0_tx
+        SI_FN_3_RX  => (OTHERS=>'0')  
       );  
+  END GENERATE;
 
   ------------------------------------------------------------------------------
   -- apertif_unb1_correlator
@@ -121,9 +125,13 @@ BEGIN
       SA_CLK      => tr_clk,
       SB_CLK      => tr_clk,
 
-      SI_FN_0_RX  => si_fn_0_tx,
-      SI_FN_1_RX  => si_fn_0_tx,
-      SI_FN_2_RX  => si_fn_0_tx,
+      SI_FN_0_RX  => emu_si_fn_0_tx_arr(0),
+      SI_FN_0_TX  => emu_si_fn_0_rx_arr(0),
+      SI_FN_1_RX  => emu_si_fn_0_tx_arr(1),
+      SI_FN_1_TX  => emu_si_fn_0_rx_arr(1),
+      SI_FN_2_RX  => emu_si_fn_0_tx_arr(2),
+      SI_FN_2_TX  => emu_si_fn_0_rx_arr(2),
+
       SI_FN_3_RX  => (OTHERS=>'0'),
 
       FN_BN_0_RX  => (OTHERS=>'0'),