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Commit 3f46972c authored by Eric Kooistra's avatar Eric Kooistra
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Added MM ports for MB II.

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boards/uniboard2/designs/unb2_test/quartus/qsys_unb2_test.qsys
+ 599
− 175
View file @ 3f46972c
......@@ -29,7 +29,7 @@
{
datum baseAddress
{
value = "57344";
value = "65536";
type = "String";
}
}
......@@ -37,7 +37,7 @@
{
datum baseAddress
{
value = "832";
value = "960";
type = "String";
}
}
......@@ -45,7 +45,7 @@
{
datum baseAddress
{
value = "49152";
value = "57344";
type = "String";
}
}
......@@ -61,7 +61,7 @@
{
datum baseAddress
{
value = "53248";
value = "61440";
type = "String";
}
}
......@@ -69,7 +69,7 @@
{
datum baseAddress
{
value = "768";
value = "896";
type = "String";
}
}
......@@ -117,7 +117,7 @@
{
datum baseAddress
{
value = "1304";
value = "1480";
type = "String";
}
}
......@@ -162,7 +162,7 @@
{
datum baseAddress
{
value = "1296";
value = "1472";
type = "String";
}
}
......@@ -194,7 +194,7 @@
{
datum baseAddress
{
value = "1216";
value = "1376";
type = "String";
}
}
......@@ -234,7 +234,7 @@
{
datum baseAddress
{
value = "32768";
value = "40960";
type = "String";
}
}
......@@ -266,23 +266,39 @@
{
datum baseAddress
{
value = "40960";
value = "49152";
type = "String";
}
}
element ram_diag_data_buffer_ddr
element ram_diag_data_buffer_ddr_MB_I
{
datum _sortIndex
{
value = "40";
value = "44";
type = "int";
}
}
element ram_diag_data_buffer_ddr.mem
element ram_diag_data_buffer_ddr_MB_I.mem
{
datum baseAddress
{
value = "24576";
value = "32768";
type = "String";
}
}
element ram_diag_data_buffer_ddr_MB_II
{
datum _sortIndex
{
value = "45";
type = "int";
}
}
element ram_diag_data_buffer_ddr_MB_II.mem
{
datum baseAddress
{
value = "16384";
type = "String";
}
}
......@@ -298,7 +314,7 @@
{
datum baseAddress
{
value = "16384";
value = "24576";
type = "String";
}
}
......@@ -314,7 +330,7 @@
{
datum baseAddress
{
value = "640";
value = "768";
type = "String";
}
}
......@@ -330,7 +346,7 @@
{
datum baseAddress
{
value = "1056";
value = "1216";
type = "String";
}
}
......@@ -346,7 +362,7 @@
{
datum baseAddress
{
value = "1088";
value = "1248";
type = "String";
}
}
......@@ -362,7 +378,7 @@
{
datum baseAddress
{
value = "256";
value = "384";
type = "String";
}
}
......@@ -375,6 +391,22 @@
}
}
element reg_diag_data_buffer_1gbe.mem
{
datum baseAddress
{
value = "640";
type = "String";
}
}
element reg_diag_data_buffer_ddr_MB_I
{
datum _sortIndex
{
value = "42";
type = "int";
}
}
element reg_diag_data_buffer_ddr_MB_I.mem
{
datum baseAddress
{
......@@ -382,19 +414,19 @@
type = "String";
}
}
element reg_diag_data_buffer_ddr
element reg_diag_data_buffer_ddr_MB_II
{
datum _sortIndex
{
value = "39";
value = "43";
type = "int";
}
}
element reg_diag_data_buffer_ddr.mem
element reg_diag_data_buffer_ddr_MB_II.mem
{
datum baseAddress
{
value = "384";
value = "128";
type = "String";
}
}
......@@ -410,7 +442,7 @@
{
datum baseAddress
{
value = "128";
value = "256";
type = "String";
}
}
......@@ -426,23 +458,39 @@
{
datum baseAddress
{
value = "1024";
value = "1184";
type = "String";
}
}
element reg_diag_rx_seq_ddr
element reg_diag_rx_seq_ddr_MB_I
{
datum _sortIndex
{
value = "38";
value = "40";
type = "int";
}
}
element reg_diag_rx_seq_ddr.mem
element reg_diag_rx_seq_ddr_MB_I.mem
{
datum baseAddress
{
value = "992";
value = "1152";
type = "String";
}
}
element reg_diag_rx_seq_ddr_MB_II
{
datum _sortIndex
{
value = "41";
type = "int";
}
}
element reg_diag_rx_seq_ddr_MB_II.mem
{
datum baseAddress
{
value = "1120";
type = "String";
}
}
......@@ -458,7 +506,7 @@
{
datum baseAddress
{
value = "896";
value = "1024";
type = "String";
}
}
......@@ -474,23 +522,39 @@
{
datum baseAddress
{
value = "1248";
value = "1424";
type = "String";
}
}
element reg_diag_tx_seq_ddr
element reg_diag_tx_seq_ddr_MB_I
{
datum _sortIndex
{
value = "37";
value = "38";
type = "int";
}
}
element reg_diag_tx_seq_ddr.mem
element reg_diag_tx_seq_ddr_MB_I.mem
{
datum baseAddress
{
value = "1232";
value = "1408";
type = "String";
}
}
element reg_diag_tx_seq_ddr_MB_II
{
datum _sortIndex
{
value = "39";
type = "int";
}
}
element reg_diag_tx_seq_ddr_MB_II.mem
{
datum baseAddress
{
value = "1392";
type = "String";
}
}
......@@ -506,7 +570,7 @@
{
datum baseAddress
{
value = "1288";
value = "1464";
type = "String";
}
}
......@@ -522,7 +586,7 @@
{
datum baseAddress
{
value = "1280";
value = "1456";
type = "String";
}
}
......@@ -538,11 +602,11 @@
{
datum baseAddress
{
value = "1120";
value = "1280";
type = "String";
}
}
element reg_io_ddr
element reg_io_ddr_MB_I
{
datum _sortIndex
{
......@@ -550,7 +614,23 @@
type = "int";
}
}
element reg_io_ddr.mem
element reg_io_ddr_MB_I.mem
{
datum baseAddress
{
value = "5767168";
type = "String";
}
}
element reg_io_ddr_MB_II
{
datum _sortIndex
{
value = "37";
type = "int";
}
}
element reg_io_ddr_MB_II.mem
{
datum baseAddress
{
......@@ -570,7 +650,7 @@
{
datum baseAddress
{
value = "1272";
value = "1448";
type = "String";
}
}
......@@ -586,7 +666,7 @@
{
datum baseAddress
{
value = "1264";
value = "1440";
type = "String";
}
}
......@@ -602,7 +682,7 @@
{
datum baseAddress
{
value = "1152";
value = "1312";
type = "String";
}
}
......@@ -666,7 +746,7 @@
{
datum baseAddress
{
value = "1184";
value = "1344";
type = "String";
}
}
......@@ -724,7 +804,7 @@
{
datum baseAddress
{
value = "960";
value = "1088";
type = "String";
}
}
......@@ -742,7 +822,7 @@
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="" />
<parameter name="projectName" value="unb2_test_ddr.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
......@@ -1148,38 +1228,73 @@
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_address"
internal="ram_diag_data_buffer_ddr.address"
name="ram_diag_data_buffer_ddr_mb_i_address"
internal="ram_diag_data_buffer_ddr_MB_I.address"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_mb_i_clk"
internal="ram_diag_data_buffer_ddr_MB_I.clk"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_mb_i_read"
internal="ram_diag_data_buffer_ddr_MB_I.read"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_mb_i_readdata"
internal="ram_diag_data_buffer_ddr_MB_I.readdata"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_mb_i_reset"
internal="ram_diag_data_buffer_ddr_MB_I.reset"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_mb_i_write"
internal="ram_diag_data_buffer_ddr_MB_I.write"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_clk"
internal="ram_diag_data_buffer_ddr.clk"
name="ram_diag_data_buffer_ddr_mb_i_writedata"
internal="ram_diag_data_buffer_ddr_MB_I.writedata"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_read"
internal="ram_diag_data_buffer_ddr.read"
name="ram_diag_data_buffer_ddr_mb_ii_address"
internal="ram_diag_data_buffer_ddr_MB_II.address"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_readdata"
internal="ram_diag_data_buffer_ddr.readdata"
name="ram_diag_data_buffer_ddr_mb_ii_clk"
internal="ram_diag_data_buffer_ddr_MB_II.clk"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_reset"
internal="ram_diag_data_buffer_ddr.reset"
name="ram_diag_data_buffer_ddr_mb_ii_read"
internal="ram_diag_data_buffer_ddr_MB_II.read"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_write"
internal="ram_diag_data_buffer_ddr.write"
name="ram_diag_data_buffer_ddr_mb_ii_readdata"
internal="ram_diag_data_buffer_ddr_MB_II.readdata"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_writedata"
internal="ram_diag_data_buffer_ddr.writedata"
name="ram_diag_data_buffer_ddr_mb_ii_reset"
internal="ram_diag_data_buffer_ddr_MB_II.reset"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_mb_ii_write"
internal="ram_diag_data_buffer_ddr_MB_II.write"
type="conduit"
dir="end" />
<interface
name="ram_diag_data_buffer_ddr_mb_ii_writedata"
internal="ram_diag_data_buffer_ddr_MB_II.writedata"
type="conduit"
dir="end" />
<interface
......@@ -1393,38 +1508,73 @@
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_address"
internal="reg_diag_data_buffer_ddr.address"
name="reg_diag_data_buffer_ddr_mb_i_address"
internal="reg_diag_data_buffer_ddr_MB_I.address"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_mb_i_clk"
internal="reg_diag_data_buffer_ddr_MB_I.clk"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_mb_i_read"
internal="reg_diag_data_buffer_ddr_MB_I.read"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_mb_i_readdata"
internal="reg_diag_data_buffer_ddr_MB_I.readdata"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_mb_i_reset"
internal="reg_diag_data_buffer_ddr_MB_I.reset"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_mb_i_write"
internal="reg_diag_data_buffer_ddr_MB_I.write"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_mb_i_writedata"
internal="reg_diag_data_buffer_ddr_MB_I.writedata"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_mb_ii_address"
internal="reg_diag_data_buffer_ddr_MB_II.address"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_clk"
internal="reg_diag_data_buffer_ddr.clk"
name="reg_diag_data_buffer_ddr_mb_ii_clk"
internal="reg_diag_data_buffer_ddr_MB_II.clk"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_read"
internal="reg_diag_data_buffer_ddr.read"
name="reg_diag_data_buffer_ddr_mb_ii_read"
internal="reg_diag_data_buffer_ddr_MB_II.read"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_readdata"
internal="reg_diag_data_buffer_ddr.readdata"
name="reg_diag_data_buffer_ddr_mb_ii_readdata"
internal="reg_diag_data_buffer_ddr_MB_II.readdata"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_reset"
internal="reg_diag_data_buffer_ddr.reset"
name="reg_diag_data_buffer_ddr_mb_ii_reset"
internal="reg_diag_data_buffer_ddr_MB_II.reset"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_write"
internal="reg_diag_data_buffer_ddr.write"
name="reg_diag_data_buffer_ddr_mb_ii_write"
internal="reg_diag_data_buffer_ddr_MB_II.write"
type="conduit"
dir="end" />
<interface
name="reg_diag_data_buffer_ddr_writedata"
internal="reg_diag_data_buffer_ddr.writedata"
name="reg_diag_data_buffer_ddr_mb_ii_writedata"
internal="reg_diag_data_buffer_ddr_MB_II.writedata"
type="conduit"
dir="end" />
<interface
......@@ -1498,38 +1648,73 @@
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_address"
internal="reg_diag_rx_seq_ddr.address"
name="reg_diag_rx_seq_ddr_mb_i_address"
internal="reg_diag_rx_seq_ddr_MB_I.address"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_clk"
internal="reg_diag_rx_seq_ddr.clk"
name="reg_diag_rx_seq_ddr_mb_i_clk"
internal="reg_diag_rx_seq_ddr_MB_I.clk"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_read"
internal="reg_diag_rx_seq_ddr.read"
name="reg_diag_rx_seq_ddr_mb_i_read"
internal="reg_diag_rx_seq_ddr_MB_I.read"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_readdata"
internal="reg_diag_rx_seq_ddr.readdata"
name="reg_diag_rx_seq_ddr_mb_i_readdata"
internal="reg_diag_rx_seq_ddr_MB_I.readdata"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_reset"
internal="reg_diag_rx_seq_ddr.reset"
name="reg_diag_rx_seq_ddr_mb_i_reset"
internal="reg_diag_rx_seq_ddr_MB_I.reset"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_write"
internal="reg_diag_rx_seq_ddr.write"
name="reg_diag_rx_seq_ddr_mb_i_write"
internal="reg_diag_rx_seq_ddr_MB_I.write"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_writedata"
internal="reg_diag_rx_seq_ddr.writedata"
name="reg_diag_rx_seq_ddr_mb_i_writedata"
internal="reg_diag_rx_seq_ddr_MB_I.writedata"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_ii_address"
internal="reg_diag_rx_seq_ddr_MB_II.address"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_ii_clk"
internal="reg_diag_rx_seq_ddr_MB_II.clk"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_ii_read"
internal="reg_diag_rx_seq_ddr_MB_II.read"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_ii_readdata"
internal="reg_diag_rx_seq_ddr_MB_II.readdata"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_ii_reset"
internal="reg_diag_rx_seq_ddr_MB_II.reset"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_ii_write"
internal="reg_diag_rx_seq_ddr_MB_II.write"
type="conduit"
dir="end" />
<interface
name="reg_diag_rx_seq_ddr_mb_ii_writedata"
internal="reg_diag_rx_seq_ddr_MB_II.writedata"
type="conduit"
dir="end" />
<interface
......@@ -1603,38 +1788,73 @@
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_address"
internal="reg_diag_tx_seq_ddr.address"
name="reg_diag_tx_seq_ddr_mb_i_address"
internal="reg_diag_tx_seq_ddr_MB_I.address"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_i_clk"
internal="reg_diag_tx_seq_ddr_MB_I.clk"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_i_read"
internal="reg_diag_tx_seq_ddr_MB_I.read"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_i_readdata"
internal="reg_diag_tx_seq_ddr_MB_I.readdata"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_i_reset"
internal="reg_diag_tx_seq_ddr_MB_I.reset"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_i_write"
internal="reg_diag_tx_seq_ddr_MB_I.write"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_clk"
internal="reg_diag_tx_seq_ddr.clk"
name="reg_diag_tx_seq_ddr_mb_i_writedata"
internal="reg_diag_tx_seq_ddr_MB_I.writedata"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_read"
internal="reg_diag_tx_seq_ddr.read"
name="reg_diag_tx_seq_ddr_mb_ii_address"
internal="reg_diag_tx_seq_ddr_MB_II.address"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_readdata"
internal="reg_diag_tx_seq_ddr.readdata"
name="reg_diag_tx_seq_ddr_mb_ii_clk"
internal="reg_diag_tx_seq_ddr_MB_II.clk"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_reset"
internal="reg_diag_tx_seq_ddr.reset"
name="reg_diag_tx_seq_ddr_mb_ii_read"
internal="reg_diag_tx_seq_ddr_MB_II.read"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_write"
internal="reg_diag_tx_seq_ddr.write"
name="reg_diag_tx_seq_ddr_mb_ii_readdata"
internal="reg_diag_tx_seq_ddr_MB_II.readdata"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_writedata"
internal="reg_diag_tx_seq_ddr.writedata"
name="reg_diag_tx_seq_ddr_mb_ii_reset"
internal="reg_diag_tx_seq_ddr_MB_II.reset"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_ii_write"
internal="reg_diag_tx_seq_ddr_MB_II.write"
type="conduit"
dir="end" />
<interface
name="reg_diag_tx_seq_ddr_mb_ii_writedata"
internal="reg_diag_tx_seq_ddr_MB_II.writedata"
type="conduit"
dir="end" />
<interface
......@@ -1739,38 +1959,73 @@
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_address"
internal="reg_io_ddr.address"
name="reg_io_ddr_mb_i_address"
internal="reg_io_ddr_MB_I.address"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_mb_i_clk"
internal="reg_io_ddr_MB_I.clk"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_mb_i_read"
internal="reg_io_ddr_MB_I.read"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_clk"
internal="reg_io_ddr.clk"
name="reg_io_ddr_mb_i_readdata"
internal="reg_io_ddr_MB_I.readdata"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_read"
internal="reg_io_ddr.read"
name="reg_io_ddr_mb_i_reset"
internal="reg_io_ddr_MB_I.reset"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_readdata"
internal="reg_io_ddr.readdata"
name="reg_io_ddr_mb_i_write"
internal="reg_io_ddr_MB_I.write"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_reset"
internal="reg_io_ddr.reset"
name="reg_io_ddr_mb_i_writedata"
internal="reg_io_ddr_MB_I.writedata"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_write"
internal="reg_io_ddr.write"
name="reg_io_ddr_mb_ii_address"
internal="reg_io_ddr_MB_II.address"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_writedata"
internal="reg_io_ddr.writedata"
name="reg_io_ddr_mb_ii_clk"
internal="reg_io_ddr_MB_II.clk"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_mb_ii_read"
internal="reg_io_ddr_MB_II.read"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_mb_ii_readdata"
internal="reg_io_ddr_MB_II.readdata"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_mb_ii_reset"
internal="reg_io_ddr_MB_II.reset"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_mb_ii_write"
internal="reg_io_ddr_MB_II.write"
type="conduit"
dir="end" />
<interface
name="reg_io_ddr_mb_ii_writedata"
internal="reg_io_ddr_MB_II.writedata"
type="conduit"
dir="end" />
<interface
......@@ -2120,7 +2375,7 @@
<parameter name="dataAddrWidth" value="23" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x80' end='0x100' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_ddr.mem' start='0x180' end='0x200' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x200' end='0x280' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x280' end='0x300' /><slave name='avs_eth_1.mms_reg' start='0x300' end='0x340' /><slave name='avs_eth_0.mms_reg' start='0x340' end='0x380' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x380' end='0x3C0' /><slave name='timer_0.s1' start='0x3C0' end='0x3E0' /><slave name='reg_diag_rx_seq_ddr.mem' start='0x3E0' end='0x400' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x400' end='0x420' /><slave name='reg_diag_bg_10gbe.mem' start='0x420' end='0x440' /><slave name='reg_diag_bg_1gbe.mem' start='0x440' end='0x460' /><slave name='reg_epcs.mem' start='0x460' end='0x480' /><slave name='reg_remu.mem' start='0x480' end='0x4A0' /><slave name='reg_unb_sens.mem' start='0x4A0' end='0x4C0' /><slave name='pio_wdi.s1' start='0x4C0' end='0x4D0' /><slave name='reg_diag_tx_seq_ddr.mem' start='0x4D0' end='0x4E0' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x4E0' end='0x4F0' /><slave name='reg_mmdp_data.mem' start='0x4F0' end='0x4F8' /><slave name='reg_mmdp_ctrl.mem' start='0x4F8' end='0x500' /><slave name='reg_dpmm_data.mem' start='0x500' end='0x508' /><slave name='reg_dpmm_ctrl.mem' start='0x508' end='0x510' /><slave name='pio_pps.mem' start='0x510' end='0x518' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x518' end='0x520' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x4000' end='0x6000' /><slave name='ram_diag_data_buffer_ddr.mem' start='0x6000' end='0x8000' /><slave name='ram_diag_bg_1gbe.mem' start='0x8000' end='0xA000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xA000' end='0xC000' /><slave name='avs_eth_0.mms_tse' start='0xC000' end='0xD000' /><slave name='avs_eth_1.mms_ram' start='0xD000' end='0xE000' /><slave name='avs_eth_0.mms_ram' start='0xE000' end='0xF000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_ddr_MB_II.mem' start='0x80' end='0x100' /><slave name='reg_diag_rx_seq_10gbe.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_10gbe.mem' start='0x180' end='0x200' /><slave name='reg_diag_data_buffer_ddr_MB_I.mem' start='0x200' end='0x280' /><slave name='reg_diag_data_buffer_1gbe.mem' start='0x280' end='0x300' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x300' end='0x380' /><slave name='avs_eth_1.mms_reg' start='0x380' end='0x3C0' /><slave name='avs_eth_0.mms_reg' start='0x3C0' end='0x400' /><slave name='reg_diag_tx_seq_10gbe.mem' start='0x400' end='0x440' /><slave name='timer_0.s1' start='0x440' end='0x460' /><slave name='reg_diag_rx_seq_ddr_MB_II.mem' start='0x460' end='0x480' /><slave name='reg_diag_rx_seq_ddr_MB_I.mem' start='0x480' end='0x4A0' /><slave name='reg_diag_rx_seq_1gbe.mem' start='0x4A0' end='0x4C0' /><slave name='reg_diag_bg_10gbe.mem' start='0x4C0' end='0x4E0' /><slave name='reg_diag_bg_1gbe.mem' start='0x4E0' end='0x500' /><slave name='reg_epcs.mem' start='0x500' end='0x520' /><slave name='reg_remu.mem' start='0x520' end='0x540' /><slave name='reg_unb_sens.mem' start='0x540' end='0x560' /><slave name='pio_wdi.s1' start='0x560' end='0x570' /><slave name='reg_diag_tx_seq_ddr_MB_II.mem' start='0x570' end='0x580' /><slave name='reg_diag_tx_seq_ddr_MB_I.mem' start='0x580' end='0x590' /><slave name='reg_diag_tx_seq_1gbe.mem' start='0x590' end='0x5A0' /><slave name='reg_mmdp_data.mem' start='0x5A0' end='0x5A8' /><slave name='reg_mmdp_ctrl.mem' start='0x5A8' end='0x5B0' /><slave name='reg_dpmm_data.mem' start='0x5B0' end='0x5B8' /><slave name='reg_dpmm_ctrl.mem' start='0x5B8' end='0x5C0' /><slave name='pio_pps.mem' start='0x5C0' end='0x5C8' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5C8' end='0x5D0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' /><slave name='ram_diag_data_buffer_ddr_MB_II.mem' start='0x4000' end='0x6000' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x6000' end='0x8000' /><slave name='ram_diag_data_buffer_ddr_MB_I.mem' start='0x8000' end='0xA000' /><slave name='ram_diag_bg_1gbe.mem' start='0xA000' end='0xC000' /><slave name='ram_diag_data_buffer_1gbe.mem' start='0xC000' end='0xE000' /><slave name='avs_eth_0.mms_tse' start='0xE000' end='0xF000' /><slave name='avs_eth_1.mms_ram' start='0xF000' end='0x10000' /><slave name='avs_eth_0.mms_ram' start='0x10000' end='0x11000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_io_ddr_MB_II.mem' start='0x40000' end='0x80000' /><slave name='ram_diag_bg_10gbe.mem' start='0x80000' end='0x100000' /><slave name='reg_tr_10GbE_back1.mem' start='0x100000' end='0x200000' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' /><slave name='reg_tr_10GbE_back0.mem' start='0x400000' end='0x500000' /><slave name='ram_diag_data_buffer_10gbe.mem' start='0x500000' end='0x580000' /><slave name='reg_io_ddr_MB_I.mem' start='0x580000' end='0x5C0000' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
......@@ -2385,7 +2640,16 @@
<parameter name="g_dat_w" value="32" />
</module>
<module
name="ram_diag_data_buffer_ddr"
name="ram_diag_data_buffer_ddr_MB_I"
kind="avs_common_mm"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="11" />
<parameter name="g_dat_w" value="32" />
</module>
<module
name="ram_diag_data_buffer_ddr_MB_II"
kind="avs_common_mm"
version="1.0"
enabled="1">
......@@ -2448,7 +2712,16 @@
<parameter name="g_dat_w" value="32" />
</module>
<module
name="reg_diag_data_buffer_ddr"
name="reg_diag_data_buffer_ddr_MB_I"
kind="avs_common_mm"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="5" />
<parameter name="g_dat_w" value="32" />
</module>
<module
name="reg_diag_data_buffer_ddr_MB_II"
kind="avs_common_mm"
version="1.0"
enabled="1">
......@@ -2475,7 +2748,16 @@
<parameter name="g_dat_w" value="32" />
</module>
<module
name="reg_diag_rx_seq_ddr"
name="reg_diag_rx_seq_ddr_MB_I"
kind="avs_common_mm"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
</module>
<module
name="reg_diag_rx_seq_ddr_MB_II"
kind="avs_common_mm"
version="1.0"
enabled="1">
......@@ -2502,7 +2784,16 @@
<parameter name="g_dat_w" value="32" />
</module>
<module
name="reg_diag_tx_seq_ddr"
name="reg_diag_tx_seq_ddr_MB_I"
kind="avs_common_mm"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="2" />
<parameter name="g_dat_w" value="32" />
</module>
<module
name="reg_diag_tx_seq_ddr_MB_II"
kind="avs_common_mm"
version="1.0"
enabled="1">
......@@ -2525,7 +2816,16 @@
<parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
</module>
<module name="reg_io_ddr" kind="avs_common_mm" version="1.0" enabled="1">
<module name="reg_io_ddr_MB_I" kind="avs_common_mm" version="1.0" enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="16" />
<parameter name="g_dat_w" value="32" />
</module>
<module
name="reg_io_ddr_MB_II"
kind="avs_common_mm"
version="1.0"
enabled="1">
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
<parameter name="g_adr_w" value="16" />
<parameter name="g_dat_w" value="32" />
......@@ -2605,7 +2905,7 @@
start="cpu_0.data_master"
end="jtag_uart_0.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0518" />
<parameter name="baseAddress" value="0x05c8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2623,7 +2923,7 @@
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04a0" />
<parameter name="baseAddress" value="0x0540" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2650,7 +2950,7 @@
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0510" />
<parameter name="baseAddress" value="0x05c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2668,7 +2968,7 @@
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0480" />
<parameter name="baseAddress" value="0x0520" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2677,7 +2977,7 @@
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0460" />
<parameter name="baseAddress" value="0x0500" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2686,7 +2986,7 @@
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0508" />
<parameter name="baseAddress" value="0x05b8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2695,7 +2995,7 @@
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0500" />
<parameter name="baseAddress" value="0x05b0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2704,7 +3004,7 @@
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04f8" />
<parameter name="baseAddress" value="0x05a8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2713,7 +3013,7 @@
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04f0" />
<parameter name="baseAddress" value="0x05a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2731,7 +3031,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0280" />
<parameter name="baseAddress" value="0x0300" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2740,7 +3040,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0200" />
<parameter name="baseAddress" value="0x0280" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2749,7 +3049,7 @@
start="cpu_0.data_master"
end="ram_diag_data_buffer_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0xa000" />
<parameter name="baseAddress" value="0xc000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2758,7 +3058,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0440" />
<parameter name="baseAddress" value="0x04e0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2767,7 +3067,7 @@
start="cpu_0.data_master"
end="ram_diag_bg_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8000" />
<parameter name="baseAddress" value="0xa000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2792,27 +3092,27 @@
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_diag_data_buffer_ddr.mem">
end="reg_diag_data_buffer_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0180" />
<parameter name="baseAddress" value="0x0200" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="ram_diag_data_buffer_ddr.mem">
end="ram_diag_data_buffer_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x6000" />
<parameter name="baseAddress" value="0x8000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_io_ddr.mem">
end="reg_io_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00040000" />
<parameter name="baseAddress" value="0x00580000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2821,7 +3121,7 @@
start="cpu_0.data_master"
end="reg_bsn_monitor_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x4000" />
<parameter name="baseAddress" value="0x6000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2830,7 +3130,7 @@
start="cpu_0.data_master"
end="reg_diag_data_buffer_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0100" />
<parameter name="baseAddress" value="0x0180" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2848,7 +3148,7 @@
start="cpu_0.data_master"
end="reg_diag_bg_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0420" />
<parameter name="baseAddress" value="0x04c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2866,7 +3166,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04e0" />
<parameter name="baseAddress" value="0x0590" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2875,7 +3175,7 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_1gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0400" />
<parameter name="baseAddress" value="0x04a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2884,7 +3184,7 @@
start="cpu_0.data_master"
end="reg_diag_tx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0380" />
<parameter name="baseAddress" value="0x0400" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2893,25 +3193,70 @@
start="cpu_0.data_master"
end="reg_diag_rx_seq_10gbe.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0080" />
<parameter name="baseAddress" value="0x0100" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_diag_tx_seq_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0580" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_diag_rx_seq_ddr_MB_I.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0480" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="ram_diag_data_buffer_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x4000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_io_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00040000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_diag_tx_seq_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0570" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_diag_tx_seq_ddr.mem">
end="reg_diag_rx_seq_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04d0" />
<parameter name="baseAddress" value="0x0460" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="15.0"
start="cpu_0.data_master"
end="reg_diag_rx_seq_ddr.mem">
end="reg_diag_data_buffer_ddr_MB_II.mem">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x03e0" />
<parameter name="baseAddress" value="0x0080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2920,7 +3265,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0xe000" />
<parameter name="baseAddress" value="0x00010000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2929,7 +3274,7 @@
start="cpu_0.data_master"
end="avs_eth_1.mms_ram">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0xd000" />
<parameter name="baseAddress" value="0xf000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2938,7 +3283,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_reg">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0340" />
<parameter name="baseAddress" value="0x03c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2947,7 +3292,7 @@
start="cpu_0.data_master"
end="avs_eth_1.mms_reg">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0300" />
<parameter name="baseAddress" value="0x0380" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2956,7 +3301,7 @@
start="cpu_0.data_master"
end="avs_eth_0.mms_tse">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0xc000" />
<parameter name="baseAddress" value="0xe000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2983,7 +3328,7 @@
start="cpu_0.data_master"
end="pio_wdi.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x04c0" />
<parameter name="baseAddress" value="0x0560" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -2992,7 +3337,7 @@
start="cpu_0.data_master"
end="timer_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x03c0" />
<parameter name="baseAddress" value="0x0440" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
......@@ -3107,13 +3452,17 @@
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_diag_data_buffer_ddr.system" />
end="reg_diag_data_buffer_ddr_MB_I.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="ram_diag_data_buffer_ddr.system" />
<connection kind="clock" version="15.0" start="clk_0.clk" end="reg_io_ddr.system" />
end="ram_diag_data_buffer_ddr_MB_I.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_io_ddr_MB_I.system" />
<connection
kind="clock"
version="15.0"
......@@ -3163,12 +3512,37 @@
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_diag_tx_seq_ddr.system" />
end="reg_diag_tx_seq_ddr_MB_I.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_diag_rx_seq_ddr_MB_I.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_io_ddr_MB_II.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="ram_diag_data_buffer_ddr_MB_II.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_diag_rx_seq_ddr.system" />
end="reg_diag_tx_seq_ddr_MB_II.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_diag_rx_seq_ddr_MB_II.system" />
<connection
kind="clock"
version="15.0"
start="clk_0.clk"
end="reg_diag_data_buffer_ddr_MB_II.system" />
<connection
kind="interrupt"
version="15.0"
......@@ -3323,17 +3697,17 @@
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_diag_data_buffer_ddr.system_reset" />
end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="ram_diag_data_buffer_ddr.system_reset" />
end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_io_ddr.system_reset" />
end="reg_io_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
......@@ -3383,12 +3757,37 @@
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_diag_tx_seq_ddr.system_reset" />
end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_io_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_diag_rx_seq_ddr.system_reset" />
end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="clk_0.clk_reset"
end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
......@@ -3523,17 +3922,17 @@
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_diag_data_buffer_ddr.system_reset" />
end="reg_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="ram_diag_data_buffer_ddr.system_reset" />
end="ram_diag_data_buffer_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_io_ddr.system_reset" />
end="reg_io_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
......@@ -3583,12 +3982,37 @@
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_diag_tx_seq_ddr.system_reset" />
end="reg_diag_tx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_diag_rx_seq_ddr_MB_I.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_io_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="ram_diag_data_buffer_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_diag_tx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_diag_rx_seq_ddr_MB_II.system_reset" />
<connection
kind="reset"
version="15.0"
start="cpu_0.debug_reset_request"
end="reg_diag_rx_seq_ddr.system_reset" />
end="reg_diag_data_buffer_ddr_MB_II.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
......
boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+ 127
− 62
View file @ 3f46972c
......@@ -174,20 +174,35 @@ ENTITY mmm_unb2_test IS
reg_tr_10GbE_back1_mosi : OUT t_mem_mosi;
reg_tr_10GbE_back1_miso : IN t_mem_miso;
-- DDR
reg_diag_tx_seq_ddr_mosi : OUT t_mem_mosi;
reg_diag_tx_seq_ddr_miso : IN t_mem_miso;
-- DDR4 : MB I
reg_io_ddr_MB_I_mosi : OUT t_mem_mosi;
reg_io_ddr_MB_I_miso : IN t_mem_miso;
reg_diag_tx_seq_ddr_MB_I_mosi : OUT t_mem_mosi;
reg_diag_tx_seq_ddr_MB_I_miso : IN t_mem_miso;
reg_diag_rx_seq_ddr_mosi : OUT t_mem_mosi;
reg_diag_rx_seq_ddr_miso : IN t_mem_miso;
reg_diag_rx_seq_ddr_MB_I_mosi : OUT t_mem_mosi;
reg_diag_rx_seq_ddr_MB_I_miso : IN t_mem_miso;
reg_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
reg_diag_data_buf_ddr_miso : IN t_mem_miso;
ram_diag_data_buf_ddr_mosi : OUT t_mem_mosi;
ram_diag_data_buf_ddr_miso : IN t_mem_miso;
reg_diag_data_buf_ddr_MB_I_mosi : OUT t_mem_mosi;
reg_diag_data_buf_ddr_MB_I_miso : IN t_mem_miso;
ram_diag_data_buf_ddr_MB_I_mosi : OUT t_mem_mosi;
ram_diag_data_buf_ddr_MB_I_miso : IN t_mem_miso;
-- DDR4 : MB II
reg_io_ddr_MB_II_mosi : OUT t_mem_mosi;
reg_io_ddr_MB_II_miso : IN t_mem_miso;
reg_io_ddr_mosi : OUT t_mem_mosi;
reg_io_ddr_miso : IN t_mem_miso
reg_diag_tx_seq_ddr_MB_II_mosi : OUT t_mem_mosi;
reg_diag_tx_seq_ddr_MB_II_miso : IN t_mem_miso;
reg_diag_rx_seq_ddr_MB_II_mosi : OUT t_mem_mosi;
reg_diag_rx_seq_ddr_MB_II_miso : IN t_mem_miso;
reg_diag_data_buf_ddr_MB_II_mosi : OUT t_mem_mosi;
reg_diag_data_buf_ddr_MB_II_miso : IN t_mem_miso;
ram_diag_data_buf_ddr_MB_II_mosi : OUT t_mem_mosi;
ram_diag_data_buf_ddr_MB_II_miso : IN t_mem_miso
);
END mmm_unb2_test;
......@@ -327,18 +342,28 @@ BEGIN
u_mm_file_reg_diag_rx_seq_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_10GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_10GbE_mosi, reg_diag_rx_seq_10GbE_miso);
u_mm_file_reg_diag_tx_seq_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR")
PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_mosi, reg_diag_tx_seq_ddr_miso);
u_mm_file_reg_diag_rx_seq_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR")
PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_mosi, reg_diag_rx_seq_ddr_miso);
u_mm_file_reg_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_mosi, reg_diag_data_buf_ddr_miso);
u_mm_file_ram_diag_data_buffer_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_mosi, ram_diag_data_buf_ddr_miso);
u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
PORT MAP(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
u_mm_file_reg_io_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_I")
PORT MAP(mm_rst, mm_clk, reg_io_ddr_MB_I_mosi, reg_io_ddr_MB_I_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_I")
PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_I_mosi, reg_diag_tx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_I")
PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_I_mosi, reg_diag_rx_seq_ddr_MB_I_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_I")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_I_mosi, reg_diag_data_buf_ddr_MB_I_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_I : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_I")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_I_mosi, ram_diag_data_buf_ddr_MB_I_miso);
u_mm_file_reg_io_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR_MB_II")
PORT MAP(mm_rst, mm_clk, reg_io_ddr_MB_II_mosi, reg_io_ddr_MB_II_miso);
u_mm_file_reg_diag_tx_seq_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_TX_SEQ_DDR_MB_II")
PORT MAP(mm_rst, mm_clk, reg_diag_tx_seq_ddr_MB_II_mosi, reg_diag_tx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_rx_seq_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ_DDR_MB_II")
PORT MAP(mm_rst, mm_clk, reg_diag_rx_seq_ddr_MB_II_mosi, reg_diag_rx_seq_ddr_MB_II_miso);
u_mm_file_reg_diag_data_buffer_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER_DDR_MB_II")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_ddr_MB_II_mosi, reg_diag_data_buf_ddr_MB_II_miso);
u_mm_file_ram_diag_data_buffer_ddr_MB_II : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_DDR_MB_II")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_ddr_MB_II_mosi, ram_diag_data_buf_ddr_MB_II_miso);
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_eth0_reg_mosi, eth1g_eth0_reg_miso);
......@@ -668,45 +693,85 @@ BEGIN
ram_diag_bg_10GbE_read_export => ram_diag_bg_10GbE_mosi.rd,
ram_diag_bg_10GbE_readdata_export => ram_diag_bg_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_reset_export => OPEN,
reg_diag_tx_seq_ddr_clk_export => OPEN,
reg_diag_tx_seq_ddr_address_export => reg_diag_tx_seq_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
reg_diag_tx_seq_ddr_write_export => reg_diag_tx_seq_ddr_mosi.wr,
reg_diag_tx_seq_ddr_writedata_export => reg_diag_tx_seq_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_read_export => reg_diag_tx_seq_ddr_mosi.rd,
reg_diag_tx_seq_ddr_readdata_export => reg_diag_tx_seq_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_rx_seq_ddr_reset_export => OPEN,
reg_diag_rx_seq_ddr_clk_export => OPEN,
reg_diag_rx_seq_ddr_address_export => reg_diag_rx_seq_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
reg_diag_rx_seq_ddr_write_export => reg_diag_rx_seq_ddr_mosi.wr,
reg_diag_rx_seq_ddr_writedata_export => reg_diag_rx_seq_ddr_mosi.wrdata(c_word_w-1 downto 0),
reg_diag_rx_seq_ddr_read_export => reg_diag_rx_seq_ddr_mosi.rd,
reg_diag_rx_seq_ddr_readdata_export => reg_diag_rx_seq_ddr_miso.rddata(c_word_w-1 downto 0),
reg_diag_data_buffer_ddr_reset_export => OPEN,
reg_diag_data_buffer_ddr_clk_export => OPEN,
reg_diag_data_buffer_ddr_address_export => reg_diag_data_buf_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_write_export => reg_diag_data_buf_ddr_mosi.wr,
reg_diag_data_buffer_ddr_writedata_export => reg_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_read_export => reg_diag_data_buf_ddr_mosi.rd,
reg_diag_data_buffer_ddr_readdata_export => reg_diag_data_buf_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_clk_export => OPEN,
ram_diag_data_buffer_ddr_reset_export => OPEN,
ram_diag_data_buffer_ddr_address_export => ram_diag_data_buf_ddr_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_write_export => ram_diag_data_buf_ddr_mosi.wr,
ram_diag_data_buffer_ddr_writedata_export => ram_diag_data_buf_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_read_export => ram_diag_data_buf_ddr_mosi.rd,
ram_diag_data_buffer_ddr_readdata_export => ram_diag_data_buf_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
reg_io_ddr_address_export => reg_io_ddr_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
reg_io_ddr_clk_export => OPEN,
reg_io_ddr_read_export => reg_io_ddr_mosi.rd,
reg_io_ddr_readdata_export => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
reg_io_ddr_reset_export => OPEN,
reg_io_ddr_write_export => reg_io_ddr_mosi.wr,
reg_io_ddr_writedata_export => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0)
reg_io_ddr_MB_I_address_export => reg_io_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
reg_io_ddr_MB_I_clk_export => OPEN,
reg_io_ddr_MB_I_read_export => reg_io_ddr_MB_I_mosi.rd,
reg_io_ddr_MB_I_readdata_export => reg_io_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
reg_io_ddr_MB_I_reset_export => OPEN,
reg_io_ddr_MB_I_write_export => reg_io_ddr_MB_I_mosi.wr,
reg_io_ddr_MB_I_writedata_export => reg_io_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_io_ddr_MB_II_address_export => reg_io_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_io_ddr_adr_w-1 DOWNTO 0),
reg_io_ddr_MB_II_clk_export => OPEN,
reg_io_ddr_MB_II_read_export => reg_io_ddr_MB_II_mosi.rd,
reg_io_ddr_MB_II_readdata_export => reg_io_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
reg_io_ddr_MB_II_reset_export => OPEN,
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w-1 downto 0),
reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_address_export => reg_diag_rx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_I_write_export => reg_diag_rx_seq_ddr_MB_I_mosi.wr,
reg_diag_rx_seq_ddr_MB_I_writedata_export => reg_diag_rx_seq_ddr_MB_I_mosi.wrdata(c_word_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_I_read_export => reg_diag_rx_seq_ddr_MB_I_mosi.rd,
reg_diag_rx_seq_ddr_MB_I_readdata_export => reg_diag_rx_seq_ddr_MB_I_miso.rddata(c_word_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_II_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_II_clk_export => OPEN,
reg_diag_rx_seq_ddr_MB_II_address_export => reg_diag_rx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_rx_seq_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_II_write_export => reg_diag_rx_seq_ddr_MB_II_mosi.wr,
reg_diag_rx_seq_ddr_MB_II_writedata_export => reg_diag_rx_seq_ddr_MB_II_mosi.wrdata(c_word_w-1 downto 0),
reg_diag_rx_seq_ddr_MB_II_read_export => reg_diag_rx_seq_ddr_MB_II_mosi.rd,
reg_diag_rx_seq_ddr_MB_II_readdata_export => reg_diag_rx_seq_ddr_MB_II_miso.rddata(c_word_w-1 downto 0),
reg_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
reg_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
reg_diag_data_buffer_ddr_MB_I_address_export => reg_diag_data_buf_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_I_write_export => reg_diag_data_buf_ddr_MB_I_mosi.wr,
reg_diag_data_buffer_ddr_MB_I_writedata_export => reg_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_I_read_export => reg_diag_data_buf_ddr_MB_I_mosi.rd,
reg_diag_data_buffer_ddr_MB_I_readdata_export => reg_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
reg_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
reg_diag_data_buffer_ddr_MB_II_address_export => reg_diag_data_buf_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_II_write_export => reg_diag_data_buf_ddr_MB_II_mosi.wr,
reg_diag_data_buffer_ddr_MB_II_writedata_export => reg_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buffer_ddr_MB_II_read_export => reg_diag_data_buf_ddr_MB_II_mosi.rd,
reg_diag_data_buffer_ddr_MB_II_readdata_export => reg_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_MB_I_clk_export => OPEN,
ram_diag_data_buffer_ddr_MB_I_reset_export => OPEN,
ram_diag_data_buffer_ddr_MB_I_address_export => ram_diag_data_buf_ddr_MB_I_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_MB_I_write_export => ram_diag_data_buf_ddr_MB_I_mosi.wr,
ram_diag_data_buffer_ddr_MB_I_writedata_export => ram_diag_data_buf_ddr_MB_I_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_MB_I_read_export => ram_diag_data_buf_ddr_MB_I_mosi.rd,
ram_diag_data_buffer_ddr_MB_I_readdata_export => ram_diag_data_buf_ddr_MB_I_miso.rddata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_MB_II_clk_export => OPEN,
ram_diag_data_buffer_ddr_MB_II_reset_export => OPEN,
ram_diag_data_buffer_ddr_MB_II_address_export => ram_diag_data_buf_ddr_MB_II_mosi.address(c_ram_diag_databuffer_ddr_addr_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_MB_II_write_export => ram_diag_data_buf_ddr_MB_II_mosi.wr,
ram_diag_data_buffer_ddr_MB_II_writedata_export => ram_diag_data_buf_ddr_MB_II_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buffer_ddr_MB_II_read_export => ram_diag_data_buf_ddr_MB_II_mosi.rd,
ram_diag_data_buffer_ddr_MB_II_readdata_export => ram_diag_data_buf_ddr_MB_II_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
......
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