Added link status MM register reg_eth10g_mosi for ETH10G.

libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd

@@ -92,6 +92,9 @@ ENTITY tr_10GbE IS
     xaui_mosi           : IN  t_mem_mosi := c_mem_mosi_rst;
     xaui_miso           : OUT t_mem_miso;
     
+    reg_eth10g_mosi     : IN  t_mem_mosi := c_mem_mosi_rst;  -- ETH10G (link status register)
+    reg_eth10g_miso     : OUT t_mem_miso; 
+    
     mdio_mosi_arr       : IN  t_mem_mosi_arr(g_nof_macs-1 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);
     mdio_miso_arr       : OUT t_mem_miso_arr(g_nof_macs-1 DOWNTO 0);
 
@@ -257,6 +260,9 @@ BEGIN
     xaui_mosi        => xaui_mosi,       -- XAUI control
     xaui_miso        => xaui_miso,
     
+    reg_eth10g_mosi  => reg_eth10g_mosi, -- ETH10G (link status register)
+    reg_eth10g_miso  => reg_eth10g_miso,
+      
     -- ST
     tx_snk_in_arr    => dp_fifo_fill_tx_src_out_arr,      -- 64 bit data @ 156 MHz
     tx_snk_out_arr   => dp_fifo_fill_tx_src_in_arr ,

libraries/technology/eth_10g/tech_eth_10g.vhd

@@ -97,12 +97,15 @@ ENTITY tech_eth_10g IS
     mm_clk           : IN  STD_LOGIC;
     mm_rst           : IN  STD_LOGIC;
     
-    mac_mosi         : IN  t_mem_mosi;                    -- MAG_10G (CSR), aggregated for all g_nof_channels
+    mac_mosi         : IN  t_mem_mosi := c_mem_mosi_rst;  -- MAG_10G (CSR), aggregated for all g_nof_channels
     mac_miso         : OUT t_mem_miso; 
     
     xaui_mosi        : IN  t_mem_mosi := c_mem_mosi_rst;  -- XAUI control
     xaui_miso        : OUT t_mem_miso;
     
+    reg_eth10g_mosi  : IN  t_mem_mosi := c_mem_mosi_rst;  -- ETH10G (link status register)
+    reg_eth10g_miso  : OUT t_mem_miso; 
+    
     -- ST
     tx_snk_in_arr    : IN  t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);      -- 64 bit data @ 156 MHz
     tx_snk_out_arr   : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0); 
@@ -197,6 +200,9 @@ BEGIN
       mac_mosi         => mac_mosi,
       mac_miso         => mac_miso,
       
+      reg_eth10g_mosi  => reg_eth10g_mosi,
+      reg_eth10g_miso  => reg_eth10g_miso,
+      
       -- ST
       tx_snk_in_arr    => tx_snk_in_arr,       -- 64 bit data @ tr_ref_clk_156
       tx_snk_out_arr   => tx_snk_out_arr, 

libraries/technology/eth_10g/tech_eth_10g_arria10.vhd

@@ -58,6 +58,14 @@
 --    2 = remote fault
 --  Hence when the xgmii_link_status is OK then the other side is also OK so
 --  then it is also appropriate to release tx_snk.xon.
+--
+--  The XGMII link status can be monitored via the reg_eth10 MM register:
+--
+--    addr  data[31:0]
+--     0      [0] = tx_snk_out_arr(I).xon
+--            [1] = xgmii_tx_ready_arr(I)
+--          [3:2] = xgmii_link_status_arr(I)
+--  
 
 LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -92,6 +100,9 @@ ENTITY tech_eth_10g_arria10 IS
     mac_mosi         : IN  t_mem_mosi;         -- MAG_10G (CSR)
     mac_miso         : OUT t_mem_miso; 
     
+    reg_eth10g_mosi  : IN  t_mem_mosi;         -- ETH10G (link status register)
+    reg_eth10g_miso  : OUT t_mem_miso; 
+    
     -- ST
     tx_snk_in_arr    : IN  t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);      -- 64 bit data @ clk_156
     tx_snk_out_arr   : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0); 
@@ -108,6 +119,8 @@ END tech_eth_10g_arria10;
 
 ARCHITECTURE str OF tech_eth_10g_arria10 IS
 
+  SIGNAL i_tx_snk_out_arr      : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+  
   -- MAG_10G control status registers
   SIGNAL mac_mosi_arr          : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
   SIGNAL mac_miso_arr          : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); 
@@ -120,21 +133,33 @@ ARCHITECTURE str OF tech_eth_10g_arria10 IS
   SIGNAL xgmii_tx_ready_arr    : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);                 -- 1 bit, from PHY 10gbase_r
   SIGNAL xgmii_tx_dc_arr       : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);    -- 72 bit
   SIGNAL xgmii_rx_dc_arr       : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);    -- 72 bit
+  
+  -- Link status monitor
+  CONSTANT c_mem_reg_eth10g_adr_w     : NATURAL := 1;
+  CONSTANT c_mem_reg_eth10g_dat_w     : NATURAL := 32;
+  CONSTANT c_mem_reg_eth10g_nof_data  : NATURAL := 1;
+  CONSTANT c_mem_reg_eth10g           : t_c_mem := (c_mem_reg_rd_latency, c_mem_reg_eth10g_adr_w , c_mem_reg_eth10g_dat_w , c_mem_reg_eth10g_nof_data, 'X');
 
+  SIGNAL reg_eth10g_mosi_arr          : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+  SIGNAL reg_eth10g_miso_arr          : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); 
+  
+  SIGNAL mm_reg_eth10g_arr            : t_slv_32_arr(g_nof_channels-1 DOWNTO 0);
+  
 BEGIN
-                   
+  tx_snk_out_arr <= i_tx_snk_out_arr;
+  
   gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
   
-    tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready;  -- pass on MAC cycle accurate backpressure
+    i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready;  -- pass on MAC cycle accurate backpressure
     
     p_xon_flow_control : PROCESS(clk_156)
       VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0);
     BEGIN
       IF rising_edge(clk_156) THEN
-        tx_snk_out_arr(I).xon <= '0';
+        i_tx_snk_out_arr(I).xon <= '0';
         v_xgmii_link_status := xgmii_link_status_arr(I) AND g_link_status_check;  -- use mask to check Tx, Rx, both or none. 
         IF xgmii_tx_ready_arr(I)='1' AND v_xgmii_link_status="00" THEN
-          tx_snk_out_arr(I).xon <= '1';  -- XON when Tx PHY is ready and XGMII is ok
+          i_tx_snk_out_arr(I).xon <= '1';  -- XON when Tx PHY is ready and XGMII is ok
         END IF;
       END IF;
     END PROCESS;
@@ -196,11 +221,44 @@ BEGIN
     tx_serial_arr      => serial_tx_arr,
     rx_serial_arr      => serial_rx_arr
   );
+  
+  
+  gen_reg_eth10g : FOR I IN 0 TO g_nof_channels-1 GENERATE
+    mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);   
+    
+    u_reg_map : ENTITY common_lib.common_reg_r_w_dc
+    GENERIC MAP (
+      g_cross_clock_domain => TRUE,             
+      g_in_new_latency     => 0,                
+      g_readback           => FALSE,            
+      g_reg                => c_mem_reg_eth10g, 
+      g_init_reg           => (OTHERS => '0')   
+    )
+    PORT MAP (
+      -- Clocks and reset
+      mm_rst      => mm_rst,          
+      mm_clk      => mm_clk,          
+      st_rst      => rst_156,     
+      st_clk      => clk_156,     
+      
+      -- Memory Mapped Slave in mm_clk domain
+      sla_in      => reg_eth10g_mosi_arr(I), 
+      sla_out     => reg_eth10g_miso_arr(I), 
+      
+      -- MM registers in st_clk domain
+      reg_wr_arr  => OPEN,          
+      reg_rd_arr  => OPEN,          
+      in_new      => '1',           
+      in_reg      => mm_reg_eth10g_arr(I), 
+      out_reg     => OPEN           
+    );
+  END GENERATE;
+  
     
   -----------------------------------------------------------------------------
   -- MM bus mux
   -----------------------------------------------------------------------------
-  u_common_mem_mux : ENTITY common_lib.common_mem_mux
+  u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
   GENERIC MAP (    
     g_nof_mosi    => g_nof_channels,
     g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10) 
@@ -212,4 +270,16 @@ BEGIN
     miso_arr => mac_miso_arr
   );  
 
+  u_common_mem_mux_eth10g : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_channels,
+    g_mult_addr_w => c_mem_reg_eth10g_adr_w 
+  )
+  PORT MAP (
+    mosi     => reg_eth10g_mosi,
+    miso     => reg_eth10g_miso,
+    mosi_arr => reg_eth10g_mosi_arr,
+    miso_arr => reg_eth10g_miso_arr
+  );  
+  
 END str;