add hdl_lib_excludes, especially exclude ip_arria10_ddr4_8g_2400.

boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr/hdllib.cfg

@@ -2,9 +2,17 @@ hdl_lib_name = unb2_test_ddr
 hdl_library_clause_name = unb2_test_ddr_lib
 hdl_lib_uses_synth = common mm technology unb2_board unb2_test
 hdl_lib_uses_sim = 
-hdl_lib_excludes = ip_arria10_mac_10g
-
 hdl_lib_technology = ip_arria10
+hdl_lib_excludes = ip_arria10_ddio
+                   ip_arria10_tse_sgmii_gx
+                   ip_arria10_pll_xgmii_mac_clocks
+                   ip_arria10_mac_10g
+                   ip_arria10_phy_10gbase_r
+                   ip_arria10_phy_10gbase_r_24
+                   ip_arria10_transceiver_pll_10g
+                   ip_arria10_transceiver_reset_controller_1
+                   ip_arria10_transceiver_reset_controller_24
+                   ip_arria10_ddr4_8g_2400
 
 synth_files =
     unb2_test_ddr.vhd