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libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd 0 → 100644
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View file @ f7edcb47
-------------------------------------------------------------------------------
--
-- Copyright (C) 2010
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_lfsr_sequences_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
-- Usage:
-- > as 10
-- > run -all
-- . Observe in_sosi and out_sosi in the Wave window
--
-- Description:
-- . This tb_ss for the subband select (SS) self verifies the data, sync and BSN
-- . The flow control is selected via g_mode_in_en and g_mode_out_ready.
--
-- Remark:
-- . Use tb_tb_ss for multi-tb DUT verification.
ENTITY tb_ss IS
GENERIC (
-- Flow control
g_mode_in_en : NATURAL := 0; -- use 0 for active in_sosi.valid control
-- use 1 for random in_sosi.valid control
g_mode_out_ready : NATURAL := 0; -- use 0 for active out_siso.ready control
-- use 1 for toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- use 2 for inverted toggling out_siso.ready control, requires g_nof_ch_sel <= g_nof_ch_in/2
-- Test duration
g_nof_sync : NATURAL := 10;
-- Functional parameters
g_reverse_ss_map : BOOLEAN := TRUE; -- use true to verify that the last data written can be read immediately after the SS page swap
--g_nof_ch_in : NATURAL := 256;
g_nof_ch_in : NATURAL := 16;
--g_nof_ch_sel : NATURAL := 192;
--g_nof_ch_sel : NATURAL := 16;
g_nof_ch_sel : NATURAL := 12;
--g_nof_ch_sel : NATURAL := 8;
--g_nof_ch_sel : NATURAL := 7;
g_use_complex : BOOLEAN := TRUE;
g_use_output_rl_adapter : BOOLEAN := FALSE -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
);
END tb_ss;
ARCHITECTURE tb OF tb_ss IS
CONSTANT clk_period : TIME := 10 ns;
CONSTANT c_rl : NATURAL := 1;
CONSTANT c_dsp_data_w : NATURAL := 16;
CONSTANT c_bsn_init : NATURAL := 10;
CONSTANT c_nof_ch_gap : NATURAL := g_nof_ch_in-g_nof_ch_sel+1;
CONSTANT c_nof_block_per_sync : NATURAL := 4;
CONSTANT c_bsn_offset : NATURAL := c_bsn_init MOD c_nof_block_per_sync;
SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1';
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL mm_reverse_mosi : t_mem_mosi;
SIGNAL mm_dut_mosi : t_mem_mosi;
SIGNAL mm_done : STD_LOGIC;
SIGNAL random_0 : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
SIGNAL toggle : STD_LOGIC := '1';
SIGNAL verify_en : STD_LOGIC := '0';
SIGNAL verify_bsn : STD_LOGIC := '1';
SIGNAL st_en : STD_LOGIC := '1';
SIGNAL st_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL st_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bsn : NATURAL := c_bsn_init;
SIGNAL dp_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL reverse_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL in_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL out_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL out_sosi : t_dp_sosi;
SIGNAL prev_out_sosi : t_dp_sosi;
SIGNAL hold_out_sosi : t_dp_sosi;
SIGNAL first_in_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
SIGNAL first_out_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
BEGIN
clk <= NOT clk OR tb_end AFTER clk_period/2;
rst <= '1', '0' AFTER clk_period*5;
------------------------------------------------------------------------------
-- Write SS select map
------------------------------------------------------------------------------
p_mm_dut_stimuli : PROCESS
BEGIN
mm_dut_mosi <= c_mem_mosi_rst;
mm_done <= '0';
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
FOR I IN 0 TO g_nof_ch_sel-1 LOOP
IF g_reverse_ss_map=FALSE THEN
proc_mem_mm_bus_wr(I, I, clk, mm_dut_mosi); -- Write the default SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (0, 1, 2, ... g_nof_ch_sel-1)
ELSE
proc_mem_mm_bus_wr(I, g_nof_ch_sel-1-I, clk, mm_dut_mosi); -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_sel-1) ==> (g_nof_ch_sel-1, ..., 2, 1, 0)
END IF;
END LOOP;
mm_done <= '1';
WAIT;
END PROCESS;
------------------------------------------------------------------------------
-- Flow control : Fixed, toggle or random
------------------------------------------------------------------------------
random_0 <= func_common_random(random_0) WHEN rising_edge(clk);
toggle <= NOT toggle WHEN rising_edge(clk);
-- Input valid
st_en <= '1' WHEN g_mode_in_en=0 ELSE random_0(random_0'HIGH);
-- Output ready
-- . toggle ready to model flow control for a dual input multiplexer, use g_nof_ch_sel < g_nof_ch_in/2
out_siso.ready <= '1' WHEN g_mode_out_ready=0 ELSE
toggle WHEN g_mode_out_ready=1 ELSE
NOT toggle;
------------------------------------------------------------------------------
-- Generate input data blocks
------------------------------------------------------------------------------
p_st_stimuli : PROCESS
VARIABLE v_re : NATURAL := 0;
VARIABLE v_im : NATURAL := 1;
VARIABLE v_data : NATURAL := 2;
BEGIN
st_sosi <= c_dp_sosi_rst;
proc_common_wait_until_high(clk, mm_done);
-- Run some sync intervals with DSP counter data for the real and imag fields
WAIT UNTIL rising_edge(clk);
FOR I IN 0 TO g_nof_sync-1 LOOP
IF g_use_complex THEN
proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
ELSE
proc_dp_gen_block_data(c_rl, TRUE, c_nof_complex*c_dsp_data_w, c_nof_complex*c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '1', "0", clk, st_en, st_siso, st_sosi); -- next sync
v_data := v_data + g_nof_ch_in;
END IF;
FOR J IN 0 TO c_nof_block_per_sync-2 LOOP -- provide sop and eop for block reference
IF g_use_complex THEN
proc_dp_gen_block_data(c_rl, FALSE, c_dsp_data_w, c_dsp_data_w, 0, v_re, v_im, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- no sync
v_re := v_re + g_nof_ch_in;
v_im := v_im + g_nof_ch_in;
ELSE
proc_dp_gen_block_data(c_rl, TRUE, c_nof_complex*c_dsp_data_w, c_nof_complex*c_dsp_data_w, v_data, 0, 0, g_nof_ch_in, 0, 0, '0', "0", clk, st_en, st_siso, st_sosi); -- next sync
v_data := v_data + g_nof_ch_in;
END IF;
END LOOP;
END LOOP;
st_sosi <= c_dp_sosi_rst;
proc_common_wait_some_cycles(clk, 3*g_nof_ch_in);
tb_end <= '1';
WAIT;
END PROCESS;
-- Time stimuli
bsn <= bsn + 1 WHEN rising_edge(clk) AND (st_sosi.eop='1');
-- Add BSN to the ST data
p_dp_sosi : PROCESS(st_sosi, bsn)
BEGIN
dp_sosi <= st_sosi;
dp_sosi.bsn <= TO_DP_BSN(bsn);
END PROCESS;
------------------------------------------------------------------------------
-- Compensate for reverse order read out of DUT so that proc_verify_* have incrementing data
------------------------------------------------------------------------------
gen_reverse_ss : IF g_reverse_ss_map=TRUE GENERATE
p_mm_reverse_stimuli : PROCESS
BEGIN
mm_reverse_mosi <= c_mem_mosi_rst;
proc_common_wait_until_low(clk, rst);
proc_common_wait_some_cycles(clk, 10);
FOR I IN 0 TO g_nof_ch_in-1 LOOP
proc_mem_mm_bus_wr(I, g_nof_ch_in-1-I, clk, mm_reverse_mosi); -- Write the reverse SS map: (0, 1, 2, ... g_nof_ch_in-1) ==> (g_nof_ch_in-1, ..., 2, 1, 0)
END LOOP;
WAIT;
END PROCESS;
u_reverse_ss : ENTITY work.ss
GENERIC MAP (
g_use_output_rl_adapter => g_use_output_rl_adapter,
g_dsp_data_w => c_dsp_data_w,
g_nof_ch_in => g_nof_ch_in,
g_nof_ch_sel => g_nof_ch_in,
g_use_complex => g_use_complex
)
PORT MAP (
mm_rst => rst,
mm_clk => clk,
dp_rst => rst,
dp_clk => clk,
-- Memory Mapped
ram_ss_ss_mosi => mm_reverse_mosi,
ram_ss_ss_miso => OPEN,
-- Streaming
input_sosi => dp_sosi,
output_sosi => reverse_sosi,
output_siso => c_dp_siso_rdy
);
END GENERATE;
------------------------------------------------------------------------------
-- DUT : SS
------------------------------------------------------------------------------
in_sosi <= dp_sosi WHEN g_reverse_ss_map=FALSE ELSE reverse_sosi;
u_dut_ss : ENTITY work.ss
GENERIC MAP (
g_use_output_rl_adapter => g_use_output_rl_adapter,
g_dsp_data_w => c_dsp_data_w,
g_nof_ch_in => g_nof_ch_in,
g_nof_ch_sel => g_nof_ch_sel,
g_use_complex => g_use_complex
)
PORT MAP (
mm_rst => rst,
mm_clk => clk,
dp_rst => rst,
dp_clk => clk,
-- Memory Mapped
ram_ss_ss_mosi => mm_dut_mosi,
ram_ss_ss_miso => OPEN,
-- Streaming
input_sosi => in_sosi,
output_sosi => out_sosi,
output_siso => out_siso
);
------------------------------------------------------------------------------
-- Verify
------------------------------------------------------------------------------
p_verify_en : PROCESS
BEGIN
verify_en <= '0';
proc_common_wait_until_high(clk, in_sosi.eop); -- now the SS will start outputing the first block
proc_common_wait_some_cycles(clk, 10); -- wait a few cycles for the SS latency
verify_en <= '1';
WAIT;
END PROCESS;
-- verify first BSN to ensure that the output BSN does not slip a frame compared to the corresponding input frame
p_verify_first_bsn : PROCESS
BEGIN
first_in_bsn <= TO_DP_BSN(c_bsn_init);
proc_common_wait_until_high(clk, out_sosi.sop);
first_out_bsn <= out_sosi.bsn;
proc_common_wait_some_cycles(clk, 1);
proc_dp_verify_value(e_equal, clk, verify_bsn, first_in_bsn, first_out_bsn);
WAIT;
END PROCESS;
-- verify incrementing next BSN and sync
proc_dp_verify_data("out_sosi.bsn", clk, verify_en, out_sosi.sop, out_sosi.bsn, prev_out_sosi.bsn);
proc_dp_verify_sync(c_nof_block_per_sync, c_bsn_offset, clk, verify_en, out_sosi.sync, out_sosi.sop, out_sosi.bsn);
-- verify incrementing re and im
gen_verify_complex: IF g_use_complex GENERATE
proc_dp_verify_data("out_sosi.re", c_unsigned_0, TO_UNSIGNED(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.re, prev_out_sosi.re);
proc_dp_verify_data("out_sosi.im", c_unsigned_0, TO_UNSIGNED(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.im, prev_out_sosi.im);
END GENERATE;
gen_verify_non_complex: IF NOT(g_use_complex) GENERATE
proc_dp_verify_data("out_sosi.data", c_unsigned_0, TO_UNSIGNED(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.data, prev_out_sosi.data);
END GENERATE;
-- verify output framing
proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sosi.sop);
END tb;
libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd 0 → 100644
+ 66
− 0
View file @ f7edcb47
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_tb_ss IS
END tb_tb_ss;
ARCHITECTURE tb OF tb_tb_ss IS
CONSTANT c_nof_sync : NATURAL := 20;
CONSTANT c_reverse_ss_map : BOOLEAN := TRUE;
BEGIN
-- > as 2
-- > run -all --> OK
-- g_mode_in_en : NATURAL := 0; -- 0 = active, 1 = random in_sosi.valid control
-- g_mode_out_ready : NATURAL := 0; -- 0 = active, 1 = toggling, 2 = inverted toggling for out_siso.ready control, toggling requires g_nof_ch_sel <= g_nof_ch_in/2
-- g_nof_sync : NATURAL := 100;
-- g_reverse_ss_map : BOOLEAN := FALSE;
-- g_nof_ch_in : NATURAL := 32;
-- g_nof_ch_sel : NATURAL := 31;
-- g_use_output_rl_adapter : BOOLEAN := FALSE; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
u_act_act_32_32 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
u_act_act_32_24 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
u_rnd_act_32_32_rl : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, TRUE);
u_rnd_act_32_32 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
u_rnd_act_32_24 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
u_act_act_32_31 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
u_rnd_act_32_31 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
u_act_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
u_rnd_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (1, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
u_act_toggle_32_15 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
u_rnd_toggle_32_15 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
u_rnd_toggle_32_15_rl : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, TRUE);
u_act_invert_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (0, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
u_rnd_invert_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (1, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
END tb;
libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd 0 → 100644
+ 66
− 0
View file @ f7edcb47
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_tb_ss IS
END tb_tb_ss;
ARCHITECTURE tb OF tb_tb_ss IS
CONSTANT c_nof_sync : NATURAL := 20;
CONSTANT c_reverse_ss_map : BOOLEAN := TRUE;
BEGIN
-- > as 2
-- > run -all --> OK
-- g_mode_in_en : NATURAL := 0; -- 0 = active, 1 = random in_sosi.valid control
-- g_mode_out_ready : NATURAL := 0; -- 0 = active, 1 = toggling, 2 = inverted toggling for out_siso.ready control, toggling requires g_nof_ch_sel <= g_nof_ch_in/2
-- g_nof_sync : NATURAL := 100;
-- g_reverse_ss_map : BOOLEAN := FALSE;
-- g_nof_ch_in : NATURAL := 32;
-- g_nof_ch_sel : NATURAL := 31;
-- g_use_output_rl_adapter : BOOLEAN := FALSE; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
u_act_act_32_32 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
u_act_act_32_24 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
u_rnd_act_32_32_rl : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, TRUE);
u_rnd_act_32_32 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
u_rnd_act_32_24 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
u_act_act_32_31 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
u_rnd_act_32_31 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
u_act_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
u_rnd_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (1, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
u_act_toggle_32_15 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
u_rnd_toggle_32_15 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
u_rnd_toggle_32_15_rl : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, TRUE);
u_act_invert_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (0, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
u_rnd_invert_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (1, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
END tb;
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