Initila commit

libraries/base/reorder/src/vhdl/reorder_rewire.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: 
+--
+-- Description:
+--
+-- Remarks:
+--
+--   
+-- Some more remarks:
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.reorder_pkg.ALL;
+
+ENTITY reorder_rewire IS
+  GENERIC( 
+    g_select_table       : t_sel_table := c_sel_table;
+    g_nof_configs        : NATURAL     := 8;
+    g_nof_input_streams  : NATURAL     := 8;
+    g_nof_output_streams : NATURAL     := 8;
+    g_sel_in_w           : NATURAL     := 3
+  );
+  PORT(
+    -- System
+    sel_in          : IN  STD_LOGIC_VECTOR(g_sel_in_w-1 DOWNTO 0) := (OTHERS => '0');  -- [2:0]
+    
+    -- Inputs from transceiver
+    input_sosi_arr  : IN  t_dp_sosi_arr(g_nof_input_streams-1 DOWNTO 0);
+    input_siso_arr  : OUT t_dp_siso_arr(g_nof_input_streams-1 DOWNTO 0);
+    
+    -- Outputs to processing
+    output_sosi_arr : OUT t_dp_sosi_arr(g_nof_output_streams-1 DOWNTO 0);
+    output_siso_arr : IN  t_dp_siso_arr(g_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy)
+   
+  );
+END reorder_rewire;
+
+ARCHITECTURE str OF reorder_rewire IS
+
+BEGIN
+  ---------------------------------------------------------------------------------------
+  -- Connect outputs in process
+  ---------------------------------------------------------------------------------------
+  PROCESS(sel_in, input_sosi_arr, output_siso_arr) 
+  BEGIN
+    FOR I IN 0 TO g_nof_output_streams-1 LOOP
+      output_sosi_arr(I) <= input_sosi_arr(g_select_table(I, TO_UINT(sel_in)));
+      input_siso_arr(g_select_table(I, TO_UINT(sel_in))) <= output_siso_arr(I);
+    END LOOP;
+  END PROCESS;
+
+--  input_siso_arr(g_nof_output_streams-1 DOWNTO 0) <= output_siso_arr;
+
+END str;