- Switched fail and ok in reg map
- Removed comments  

Removed internal DDR memory model (now needs to be instantiated in tb). Use dedicated records for DDR3 and DDR4 phy interfaces, instead of the combined record.

Removed g_use_ddr_memory_model so the DDR memory model code is not seen/needed by synthesis. Instead only support DDR memory model instantiation in test bench.

Renamed ctlr_mosi into ctlr_tech_mosi for the technology IP side to more clearly distinghuis it from ctrl_drv_mosi for the IO driver side.

splitted the terminationcontrol lines from the record types 't_tech_ddr_phy_in' and 't_tech_ddr_phy_ou'

Added g_sim_flash_model to ensure only one instance of flash model, to avoid double driver failure in sim.

Renamed key hdl_lib_uses into hdl_lib_uses_synth and added new key hdl_lib_uses_sim for extra test_bench_files library dependencies.

to quartus compile