update tb

libraries/io/ddr3/hdllib.cfg

@@ -19,6 +19,9 @@ synth_files =
     $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
     $UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_1066.vhd
     $UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_800.vhd
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master.v
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master_sim/uphy_4g_800_master.v
+
     $UNB/Firmware/modules/ddr3/src/vhdl/ddr3.vhd
     $UNB/Firmware/modules/ddr3/src/vhdl/ddr3_transpose.vhd
     $UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3.vhd
@@ -26,6 +29,15 @@ synth_files =
     $UNB/Firmware/modules/ddr3/src/vhdl/seq_ddr3.vhd
 
 test_bench_files = 
+    #$UNB/Firmware/modules/ddr3/tb/vhdl/ddr3_mem_model.vhd
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_800_mem_model.vhd
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_800_full_mem_model.vhd
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_1066_mem_model.vhd
+    $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_1066_full_mem_model.vhd
+    $UNB/Firmware/modules/ddr3/tb/vhdl/tb_ddr3.vhd
+    $UNB/Firmware/modules/ddr3/tb/vhdl/tb_mms_ddr3.vhd
+    $UNB/Firmware/modules/ddr3/tb/vhdl/tb_seq_ddr3.vhd
+    $UNB/Firmware/modules/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
 
 modelsim_search_libraries =
 # stratixiv only