Added mm ports

libraries/io/ddr3/src/vhdl/ddr3.vhd

@@ -46,7 +46,11 @@ ENTITY ddr3 IS
     g_flush_sop_start_channel : NATURAL := 0;
     g_flush_nof_channels      : NATURAL := 0
   );                      
-  PORT (                  
+  PORT (   
+    -- MM clock + reset                                                             
+    mm_rst             : IN    STD_LOGIC;                                           
+    mm_clk             : IN    STD_LOGIC;                                                          
+    
     ctlr_ref_clk       : IN    STD_LOGIC;
     ctlr_rst           : IN    STD_LOGIC; -- asynchronous reset input to controller
 

libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd

@@ -217,7 +217,11 @@ BEGIN
     g_flush_sop_start_channel => 0,    
     g_flush_nof_channels      => 0     
   )                          
-  PORT MAP (                      
+  PORT MAP (    
+  
+    mm_clk             => mm_clk, 
+    mm_rst             => mm_rst,
+                    
     ctlr_ref_clk       => dp_ref_clk,
     ctlr_rst           => dp_ref_rst,