Added mm ports

libraries/io/ddr3/src/vhdl/ddr3.vhd

@@ -47,6 +47,10 @@ ENTITY ddr3 IS
     g_flush_nof_channels      : NATURAL := 0
   );                      
   PORT (   
+    -- MM clock + reset                                                             
+    mm_rst             : IN    STD_LOGIC;                                           
+    mm_clk             : IN    STD_LOGIC;                                                          
+    
     ctlr_ref_clk       : IN    STD_LOGIC;
     ctlr_rst           : IN    STD_LOGIC; -- asynchronous reset input to controller
 

libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd

@@ -218,6 +218,10 @@ BEGIN
     g_flush_nof_channels      => 0     
   )                          
   PORT MAP (    
+  
+    mm_clk             => mm_clk, 
+    mm_rst             => mm_rst,
+                    
     ctlr_ref_clk       => dp_ref_clk,
     ctlr_rst           => dp_ref_rst,