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Commit ed5fdb06 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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update

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libraries/io/ddr3/hdllib.cfg
+ 7
− 16
View file @ ed5fdb06
......@@ -8,8 +8,8 @@ hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
#modelsim_compile_ip_files =
# $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
modelsim_compile_ip_files =
$RADIOHDL/libraries/io/ddr3/src/tcl/compile_ip.tcl
synth_files =
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_pkg.vhd
......@@ -17,12 +17,7 @@ synth_files =
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_seq.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_driver.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
$UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_1066.vhd
$UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_800.vhd
$UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master.v
$UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master_sim/uphy_4g_800_master.v
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3.vhd
src/vhdl/ddr3.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_transpose.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3_capture.vhd
......@@ -30,14 +25,10 @@ synth_files =
test_bench_files =
#$UNB/Firmware/modules/ddr3/tb/vhdl/ddr3_mem_model.vhd
$UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_800_mem_model.vhd
$UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_800_full_mem_model.vhd
$UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_1066_mem_model.vhd
$UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_1066_full_mem_model.vhd
$UNB/Firmware/modules/ddr3/tb/vhdl/tb_ddr3.vhd
$UNB/Firmware/modules/ddr3/tb/vhdl/tb_mms_ddr3.vhd
$UNB/Firmware/modules/ddr3/tb/vhdl/tb_seq_ddr3.vhd
$UNB/Firmware/modules/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
tb/vhdl/tb_ddr3.vhd
tb/vhdl/tb_mms_ddr3.vhd
tb/vhdl/tb_seq_ddr3.vhd
tb/vhdl/tb_ddr3_transpose.vhd
modelsim_search_libraries =
# stratixiv only
......
libraries/io/ddr3/src/tcl/compile_ip.tcl 0 → 100644
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− 0
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libraries/io/ddr3/src/vhdl/ddr3.vhd 0 → 100644
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libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd 0 → 100644
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--------------------------------------------------------------------------------
--
-- Copyright (C) 2011
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
-- This testbench tests the different type of DDR controllers:
--
-- - aphy_4g_800
-- - aphy_4g_1066
-- - uphy_4g_800_master
-- - uphy_4g_1066_master
-- - uphy_4g_800_slave
-- - uphy_4g_1066_slave
--
-- The DUT can be selected, using the c_phy and c_mts constants.
--
-- Testbench is selftesting:
--
-- > run -all
--
-- Known issues: The memory model used for the aphy_4g_1066 simulation
-- gives an error at the end of the write cyclus.
--
LIBRARY IEEE, common_lib, dp_lib, diagnostics_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_ddr3 IS
END ENTITY tb_ddr3;
ARCHITECTURE str of tb_ddr3 IS
CONSTANT c_phy : NATURAL := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
CONSTANT c_mts : NATURAL := 800; -- Available options: 800 and 1066
CONSTANT c_ctlr_ref_clk_per : TIME := 5 ns; --200 MHz
CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
CONSTANT c_data_w : NATURAL := 256; --32;
SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_rst : STD_LOGIC := '1';
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL ctlr_gen_clk : STD_LOGIC;
SIGNAL ctlr_gen_rst : STD_LOGIC;
SIGNAL ctlr_rdy : STD_LOGIC;
SIGNAL ctlr_init_done : STD_LOGIC;
SIGNAL dvr_start_addr : t_ddr3_addr;
SIGNAL dvr_end_addr : t_ddr3_addr;
SIGNAL dvr_en : STD_LOGIC;
SIGNAL dvr_wr_not_rd : STD_LOGIC;
SIGNAL dvr_done : STD_LOGIC;
SIGNAL wr_siso : t_dp_siso;
SIGNAL wr_sosi : t_dp_sosi;
SIGNAL wr_siso_pre_fifo : t_dp_siso;
SIGNAL wr_sosi_pre_fifo : t_dp_sosi;
SIGNAL rd_siso : t_dp_siso;
SIGNAL rd_sosi : t_dp_sosi;
SIGNAL src_diag_en : STD_LOGIC;
SIGNAL src_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL snk_diag_en : STD_LOGIC;
SIGNAL snk_diag_res : STD_LOGIC;
SIGNAL snk_diag_res_val : STD_LOGIC;
SIGNAL snk_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL flush_ena : STD_LOGIC;
BEGIN
ctlr_ref_clk <= NOT(ctlr_ref_clk) OR tb_end AFTER c_ctlr_ref_clk_per/2;
ctlr_rst <= '0' AFTER 100 ns;
dvr_start_addr <= c_ddr3_addr_lo;
dvr_end_addr <= c_ddr3_addr_hi_sim;
flush_ena <= '0';
p_stimuli : PROCESS
BEGIN
tb_end <= '0';
dvr_en <= '0';
src_diag_en <= '0';
dvr_wr_not_rd <= '0';
snk_diag_en <= '0';
WAIT UNTIL ctlr_init_done = '1';
FOR i IN 0 TO 1 LOOP
WAIT UNTIL rising_edge(ctlr_gen_clk); -- Give the driver FSM a cycle to go into idle mode
END LOOP;
-- START WRITE
src_diag_en <= '1';
dvr_wr_not_rd <= '1';
dvr_en <= '1';
WAIT UNTIL rising_edge(ctlr_gen_clk);
dvr_en <= '0';
-- WRITE DONE
WAIT UNTIL dvr_done = '1';
src_diag_en <= '0';
-- START READ
snk_diag_en <= '1';
dvr_wr_not_rd <= '0';
dvr_en <= '1';
WAIT UNTIL rising_edge(ctlr_gen_clk);
dvr_en <= '0';
-- READ DONE
WAIT UNTIL dvr_done = '1';
WAIT FOR 2 us; -- 'Done' means all requests are posted. Wait for the last read data to arrive.
ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!" SEVERITY FAILURE;
ASSERT snk_diag_res = '0' REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;
ASSERT FALSE REPORT "[OK] Test passed." SEVERITY NOTE;
tb_end <= '1';
WAIT;
END PROCESS;
u_diagnostics: ENTITY diagnostics_lib.diagnostics
GENERIC MAP (
g_dat_w => c_data_w,
g_nof_streams => 1
)
PORT MAP (
rst => ctlr_gen_rst,
clk => ctlr_gen_clk,
snk_out_arr(0) => rd_siso,
snk_in_arr(0) => rd_sosi,
snk_diag_en(0) => snk_diag_en,
snk_diag_md(0) => '1',
snk_diag_res(0) => snk_diag_res,
snk_diag_res_val(0) => snk_diag_res_val,
snk_val_cnt(0) => snk_val_cnt,
src_out_arr(0) => wr_sosi,
src_in_arr(0) => wr_siso,
src_diag_en(0) => src_diag_en,
src_diag_md(0) => '1',
src_val_cnt(0) => src_val_cnt
);
gen_uphy_4g_model : IF c_phy > 0 GENERATE
u_4gb_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
GENERIC MAP (
MEM_IF_ADDR_WIDTH => 15,
MEM_IF_ROW_ADDR_WIDTH => 15,
MEM_IF_COL_ADDR_WIDTH => 10,
MEM_IF_CS_PER_RANK => 1,
MEM_IF_CONTROL_WIDTH => 1,
MEM_IF_DQS_WIDTH => 8,
MEM_IF_CS_WIDTH => 2,
MEM_IF_BANKADDR_WIDTH => 3,
MEM_IF_DQ_WIDTH => 64,
MEM_IF_CK_WIDTH => 2,
MEM_IF_CLK_EN_WIDTH => 2,
DEVICE_WIDTH => 1,
MEM_TRCD => 6,
MEM_TRTP => 3,
MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
MEM_IF_ODT_WIDTH => 2,
MEM_MIRROR_ADDRESSING_DEC => 0,
MEM_REGDIMM_ENABLED => false,
DEVICE_DEPTH => 1,
MEM_GUARANTEED_WRITE_INIT => false,
MEM_VERBOSE => true,
MEM_INIT_EN => false,
MEM_INIT_FILE => "",
DAT_DATA_WIDTH => 32
)
PORT MAP (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
mem_ba => phy_ou.ba, -- .mem_ba
mem_ck => phy_io.clk, -- .mem_ck
mem_ck_n => phy_io.clk_n, -- .mem_ck_n
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0), -- .mem_cke
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
mem_dm => phy_ou.dm, -- .mem_dm
mem_ras_n => ras_n, -- .mem_ras_n
mem_cas_n => cas_n, -- .mem_cas_n
mem_we_n => we_n, -- .mem_we_n
mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
mem_dq => phy_io.dq, -- .mem_dq
mem_dqs => phy_io.dqs, -- .mem_dqs
mem_dqs_n => phy_io.dqs_n, -- .mem_dqs_n
mem_odt => phy_ou.odt -- .mem_odt
);
ras_n(0) <= phy_ou.ras_n;
cas_n(0) <= phy_ou.cas_n;
we_n(0) <= phy_ou.we_n;
END GENERATE;
u_ddr3_module: ENTITY work.ddr3
GENERIC MAP(
g_phy => c_phy,
g_mts => c_mts,
g_ddr => c_ddr,
g_wr_data_w => c_data_w,
g_rd_data_w => c_data_w
)
PORT MAP (
ctlr_ref_clk => ctlr_ref_clk,
ctlr_rst => ctlr_rst,
ctlr_gen_clk => ctlr_gen_clk,
ctlr_gen_rst => ctlr_gen_rst,
ctlr_init_done => ctlr_init_done,
ctlr_rdy => ctlr_rdy,
dvr_start_addr => dvr_start_addr,
dvr_end_addr => dvr_end_addr,
dvr_en => dvr_en,
dvr_wr_not_rd => dvr_wr_not_rd,
dvr_done => dvr_done,
wr_clk => ctlr_gen_clk,
wr_rst => ctlr_gen_rst,
wr_sosi => wr_sosi,
wr_siso => wr_siso,
flush_ena => flush_ena,
rd_sosi => rd_sosi,
rd_siso => rd_siso,
rd_clk => ctlr_gen_clk,
rd_rst => ctlr_gen_rst,
phy_ou => phy_ou,
phy_io => phy_io,
phy_in => phy_in
);
END ARCHITECTURE str;
libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd 0 → 100644
+ 417
− 0
View file @ ed5fdb06
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
--
-- Purpose: Testbench for the ddr3_transpose unit
-- To be used in conjunction with python testscript: ../python/tc_transpose_ddr3.py
--
--
-- Usage:
-- > as 8
-- > run -all
-- > run python script in separate terminal: "python tc_transpose_ddr3.py --unb 0 --fn 0 --sim"
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_ddr3_transpose IS
GENERIC (
g_wr_chunksize : POSITIVE := 64;
g_wr_nof_chunks : POSITIVE := 1;
g_rd_chunksize : POSITIVE := 16;
g_rd_nof_chunks : POSITIVE := 4;
g_gapsize : NATURAL := 0;
g_nof_blocks : POSITIVE := 4;
g_nof_blk_per_sync : POSITIVE := 64
);
END tb_ddr3_transpose;
ARCHITECTURE tb OF tb_ddr3_transpose IS
CONSTANT c_sim : BOOLEAN := TRUE;
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
CONSTANT c_mm_clk_period : TIME := 100 ps;
CONSTANT c_dp_clk_period : TIME := 5 ns;
CONSTANT c_dp_pps_period : NATURAL := 64;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0';
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
-- TB
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_re_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_re_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_re_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_im_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_im_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_im_miso : t_mem_miso;
-- DUT
SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_ss_ss_transp_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------------------------------------
-- Component declaration of mm_file
----------------------------------------------------------------------------
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
g_update_on_change : BOOLEAN := FALSE
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
);
END COMPONENT;
-- Compose the Constants for the DUT
CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_wr_chunksize,
g_wr_nof_chunks,
g_rd_chunksize,
g_rd_nof_chunks,
g_gapsize,
g_nof_blocks);
CONSTANT c_blocksize : POSITIVE := g_wr_nof_chunks * g_wr_chunksize;
CONSTANT c_page_size : POSITIVE := c_blocksize * g_nof_blocks;
CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
CONSTANT c_mts : NATURAL := 800;--1066; --800
CONSTANT c_phy : NATURAL := 1;
CONSTANT c_data_w : NATURAL := 64;
CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
-- Custom definitions of constants
CONSTANT c_bg_block_len : NATURAL := c_blocksize * g_rd_chunksize;
CONSTANT c_db_block_len : NATURAL := c_blocksize * g_rd_chunksize;
-- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := 4;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*8;
CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
CONSTANT c_bg_data_file_prefix : STRING := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
-- Configuration of the databuffers:
CONSTANT c_db_nof_streams : POSITIVE := 4;
CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real;
CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag;
SIGNAL bg_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL bg_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams -1 DOWNTO 0);
SIGNAL out_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- Siganls to connect the memory driver with the mm register interface
SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_rst : STD_LOGIC := '1';
SIGNAL ctlr_gen_clk : STD_LOGIC;
SIGNAL ctlr_gen_rst : STD_LOGIC;
SIGNAL ctlr_rdy : STD_LOGIC;
SIGNAL ctlr_init_done : STD_LOGIC;
SIGNAL dvr_start_addr : t_ddr3_addr;
SIGNAL dvr_end_addr : t_ddr3_addr;
SIGNAL dvr_en : STD_LOGIC;
SIGNAL dvr_wr_not_rd : STD_LOGIC;
SIGNAL dvr_done : STD_LOGIC;
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
ctlr_ref_clk <= NOT ctlr_ref_clk AFTER c_ctrl_ref_clk_period/2;
ctlr_rst <= '1', '0' AFTER c_ctrl_ref_clk_period*5;
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
-- TB
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP(
g_nof_streams => c_bg_nof_output_streams,
g_buf_dat_w => c_bg_buf_dat_w,
g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
PORT MAP(
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
en_sync => dp_pps,
-- MM interface
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso,
-- ST interface
out_siso_arr => bg_siso_arr,
out_sosi_arr => bg_sosi_arr
);
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut: ENTITY work.ddr3_transpose
GENERIC MAP(
g_sim => TRUE,
g_nof_streams => c_bg_nof_output_streams,
g_in_dat_w => c_bg_buf_dat_w/c_nof_complex,
g_frame_size_in => g_wr_chunksize,
g_frame_size_out => g_wr_chunksize,
g_nof_blk_per_sync => g_nof_blk_per_sync,
g_use_complex => TRUE,
g_ena_pre_transp => FALSE,
g_phy => c_phy,
g_mts => c_mts,
g_ddr3_seq => c_ddr3_seq_conf
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
snk_out_arr => bg_siso_arr,
snk_in_arr => bg_sosi_arr,
-- ST source
src_in_arr => out_siso_arr,
src_out_arr => out_sosi_arr,
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
ser_term_ctrl_out => OPEN,
par_term_ctrl_out => OPEN,
ser_term_ctrl_in => OPEN,
par_term_ctrl_in => OPEN,
phy_in => phy_in,
phy_io => phy_io,
phy_ou => phy_ou
);
u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
generic map (
MEM_IF_ADDR_WIDTH => 15,
MEM_IF_ROW_ADDR_WIDTH => 15,
MEM_IF_COL_ADDR_WIDTH => 10,
MEM_IF_CS_PER_RANK => 1,
MEM_IF_CONTROL_WIDTH => 1,
MEM_IF_DQS_WIDTH => 8,
MEM_IF_CS_WIDTH => 2,
MEM_IF_BANKADDR_WIDTH => 3,
MEM_IF_DQ_WIDTH => 64,
MEM_IF_CK_WIDTH => 2,
MEM_IF_CLK_EN_WIDTH => 2,
DEVICE_WIDTH => 1,
MEM_TRCD => 6,
MEM_TRTP => 3,
MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
MEM_IF_ODT_WIDTH => 2,
MEM_MIRROR_ADDRESSING_DEC => 0,
MEM_REGDIMM_ENABLED => false,
DEVICE_DEPTH => 1,
MEM_GUARANTEED_WRITE_INIT => false,
MEM_VERBOSE => true,
MEM_INIT_EN => false,
MEM_INIT_FILE => "",
DAT_DATA_WIDTH => 32
)
port map (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba,
mem_ck => phy_io.clk,
mem_ck_n => phy_io.clk_n,
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm,
mem_ras_n => ras_n,
mem_cas_n => cas_n,
mem_we_n => we_n,
mem_reset_n => phy_ou.reset_n,
mem_dq => phy_io.dq,
mem_dqs => phy_io.dqs,
mem_dqs_n => phy_io.dqs_n,
mem_odt => phy_ou.odt
);
ras_n(0) <= phy_ou.ras_n;
cas_n(0) <= phy_ou.cas_n;
we_n(0) <= phy_ou.we_n;
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf_re : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => c_db_data_type_re,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
ram_data_buf_miso => ram_diag_data_buf_re_miso,
reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
reg_data_buf_miso => reg_diag_data_buf_re_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
----------------------------------------------------------------------------
-- Sink: data buffer imag
----------------------------------------------------------------------------
u_data_buf_im : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => c_db_data_type_im,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
ram_data_buf_miso => ram_diag_data_buf_im_miso,
reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
reg_data_buf_miso => reg_diag_data_buf_im_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
END tb;
libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd 0 → 100644
+ 387
− 0
View file @ ed5fdb06
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
--
-- Purpose: Testbench for the seq_ddr3 unit
-- To be used in conjunction with python testscript: ../python/tc_seq_ddr3.py
--
--
-- Usage:
-- > as 8
-- > run -all
-- > run python script in separate terminal: "python tc_seq_ddr3.py --unb 0 --fn 0 --sim"
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_mms_ddr3 IS
END tb_mms_ddr3;
ARCHITECTURE tb OF tb_mms_ddr3 IS
CONSTANT c_sim : BOOLEAN := TRUE;
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 200 ps;
CONSTANT c_dp_clk_period : TIME := 5 ns;
CONSTANT c_dp_pps_period : NATURAL := 64;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0';
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
-- TB
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-- DUT
SIGNAL reg_ddr3_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_ddr3_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------------------------------------
-- Component declaration of mm_file
----------------------------------------------------------------------------
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
g_update_on_change : BOOLEAN := FALSE
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
);
END COMPONENT;
-- Compose the Constants for the DUT
CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
CONSTANT c_mts : NATURAL := 800;--1066; --800
CONSTANT c_phy : NATURAL := 1;
CONSTANT c_wr_data_w : NATURAL := 64;
CONSTANT c_wr_use_ctrl : BOOLEAN := FALSE;
CONSTANT c_wr_fifo_depth : NATURAL := 1024;
CONSTANT c_rd_fifo_depth : NATURAL := 256;
CONSTANT c_rd_data_w : NATURAL := 64;
CONSTANT c_flush_wr_fifo : BOOLEAN := FALSE;
CONSTANT c_flush_sop : BOOLEAN := FALSE;
CONSTANT c_flush_sop_channel : BOOLEAN := FALSE;
CONSTANT c_flush_sop_start_channel : NATURAL := 0;
CONSTANT c_flush_nof_channels : NATURAL := 0;
CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
-- Custom definitions of constants
CONSTANT c_bg_block_len : NATURAL := 1024;
CONSTANT c_db_block_len : NATURAL := 1024;
-- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := 1;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*8;
CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
CONSTANT c_bg_data_file_prefix : STRING := "../../../src/hex/tb_bg_dat";
CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 1, 1);
-- Configuration of the databuffers:
CONSTANT c_db_nof_streams : POSITIVE := 1;
CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real;
CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag;
SIGNAL bg_siso_arr : t_dp_siso_arr(1 -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL bg_sosi_arr : t_dp_sosi_arr(1 -1 DOWNTO 0);
SIGNAL out_sosi_arr : t_dp_sosi_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- Siganls to connect the memory driver with the mm register interface
SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_rst : STD_LOGIC := '1';
SIGNAL ctlr_gen_clk : STD_LOGIC;
SIGNAL ctlr_gen_rst : STD_LOGIC;
SIGNAL ctlr_rdy : STD_LOGIC;
SIGNAL ctlr_init_done : STD_LOGIC;
SIGNAL dvr_start_addr : t_ddr3_addr;
SIGNAL dvr_end_addr : t_ddr3_addr;
SIGNAL dvr_en : STD_LOGIC;
SIGNAL dvr_wr_not_rd : STD_LOGIC;
SIGNAL dvr_done : STD_LOGIC;
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL flush_ena : STD_LOGIC;
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
ctlr_ref_clk <= NOT ctlr_ref_clk AFTER c_ctrl_ref_clk_period/2;
ctlr_rst <= '1', '0' AFTER c_ctrl_ref_clk_period*5;
flush_ena <= '0';
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
-- TB
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_ram_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
u_mm_file_reg_ddr3_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DDR3_0")
PORT MAP(mm_rst, mm_clk, reg_ddr3_mosi, reg_ddr3_miso );
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP(
g_nof_streams => c_bg_nof_output_streams,
g_buf_dat_w => c_bg_buf_dat_w,
g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
PORT MAP(
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
en_sync => dp_pps,
-- MM interface
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso,
-- ST interface
out_siso_arr => bg_siso_arr,
out_sosi_arr => bg_sosi_arr
);
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut: ENTITY work.mms_ddr3
GENERIC MAP(
g_sim => c_sim,
g_ddr => c_ddr,
g_mts => c_mts,
g_phy => c_phy,
g_wr_data_w => c_wr_data_w,
g_wr_use_ctrl => c_wr_use_ctrl,
g_wr_fifo_depth => c_wr_fifo_depth,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_rd_data_w,
g_flush_wr_fifo => c_flush_wr_fifo,
g_flush_sop => c_flush_sop,
g_flush_sop_channel => c_flush_sop_channel,
g_flush_sop_start_channel => c_flush_sop_start_channel,
g_flush_nof_channels => c_flush_nof_channels
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
-- MM registers
ctrl_mosi => reg_ddr3_mosi,
ctrl_miso => reg_ddr3_miso,
ctlr_ref_clk => ctlr_ref_clk,
ctlr_rst => ctlr_rst,
ctlr_gen_clk => open,
ctlr_gen_rst => open,
wr_clk => dp_clk,
wr_rst => dp_rst,
wr_sosi => bg_sosi_arr(0),
wr_siso => bg_siso_arr(0),
flush_ena => flush_ena,
rd_sosi => out_sosi_arr(0),
rd_siso => out_siso_arr(0),
rd_clk => dp_clk,
rd_rst => dp_rst,
rd_fifo_usedw => open, -- relative to FIFO wr side
ddr3_in => phy_in,
ddr3_io => phy_io,
ddr3_ou => phy_ou
);
gen_u_800_model : IF c_phy > 0 GENERATE
u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
generic map (
MEM_IF_ADDR_WIDTH => 15,
MEM_IF_ROW_ADDR_WIDTH => 15,
MEM_IF_COL_ADDR_WIDTH => 10,
MEM_IF_CS_PER_RANK => 1,
MEM_IF_CONTROL_WIDTH => 1,
MEM_IF_DQS_WIDTH => 8,
MEM_IF_CS_WIDTH => 2,
MEM_IF_BANKADDR_WIDTH => 3,
MEM_IF_DQ_WIDTH => 64,
MEM_IF_CK_WIDTH => 2,
MEM_IF_CLK_EN_WIDTH => 2,
DEVICE_WIDTH => 1,
MEM_TRCD => 6,
MEM_TRTP => 3,
MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
MEM_IF_ODT_WIDTH => 2,
MEM_MIRROR_ADDRESSING_DEC => 0,
MEM_REGDIMM_ENABLED => false,
DEVICE_DEPTH => 1,
MEM_GUARANTEED_WRITE_INIT => false,
MEM_VERBOSE => true,
MEM_INIT_EN => false,
MEM_INIT_FILE => "",
DAT_DATA_WIDTH => 32
)
port map (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba,
mem_ck => phy_io.clk,
mem_ck_n => phy_io.clk_n,
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm,
mem_ras_n => ras_n,
mem_cas_n => cas_n,
mem_we_n => we_n,
mem_reset_n => phy_ou.reset_n,
mem_dq => phy_io.dq,
mem_dqs => phy_io.dqs,
mem_dqs_n => phy_io.dqs_n,
mem_odt => phy_ou.odt
);
ras_n(0) <= phy_ou.ras_n;
cas_n(0) <= phy_ou.cas_n;
we_n(0) <= phy_ou.we_n;
END GENERATE;
----------------------------------------------------------------------------
-- Sink: data buffer
----------------------------------------------------------------------------
u_data_buf : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => e_data,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
END tb;
libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd 0 → 100644
+ 371
− 0
View file @ ed5fdb06
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
--
-- Purpose: Testbench for the seq_ddr3 unit
-- To be used in conjunction with python testscript: ../python/tc_seq_ddr3.py
--
--
-- Usage:
-- > as 8
-- > run -all
-- > run python script in separate terminal: "python tc_seq_ddr3.py --unb 0 --fn 0 --sim"
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > Evalute the WAVE window.
LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.ddr3_pkg.ALL;
ENTITY tb_seq_ddr3 IS
GENERIC (
g_wr_chunksize : POSITIVE := 240;
g_wr_nof_chunks : POSITIVE := 1;
g_rd_chunksize : POSITIVE := 16;
g_rd_nof_chunks : POSITIVE := 15;
g_gapsize : NATURAL := 16;
g_nof_blocks : POSITIVE := 5
);
END tb_seq_ddr3;
ARCHITECTURE tb OF tb_seq_ddr3 IS
CONSTANT c_sim : BOOLEAN := TRUE;
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
CONSTANT c_mm_clk_period : TIME := 8 ns; -- 200 ps;
CONSTANT c_dp_clk_period : TIME := 5 ns;
CONSTANT c_dp_pps_period : NATURAL := 64;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC := '1';
SIGNAL mm_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0';
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
-- TB
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-- DUT
SIGNAL reg_ddr3_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_ddr3_miso : t_mem_miso := c_mem_miso_rst;
----------------------------------------------------------------------------
-- Component declaration of mm_file
----------------------------------------------------------------------------
COMPONENT mm_file
GENERIC(
g_file_prefix : STRING;
g_update_on_change : BOOLEAN := FALSE
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_master_out : OUT t_mem_mosi;
mm_master_in : IN t_mem_miso
);
END COMPONENT;
-- Compose the Constants for the DUT
CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_wr_chunksize,
g_wr_nof_chunks,
g_rd_chunksize,
g_rd_nof_chunks,
g_gapsize,
g_nof_blocks);
CONSTANT c_blocksize : POSITIVE := g_wr_nof_chunks * g_wr_chunksize;
CONSTANT c_page_size : POSITIVE := c_blocksize * g_nof_blocks;
CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
CONSTANT c_mts : NATURAL := 1066;--1066; --800
CONSTANT c_phy : NATURAL := 1;
CONSTANT c_data_w : NATURAL := 64;
CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
-- Custom definitions of constants
CONSTANT c_bg_block_len : NATURAL := c_page_size;
CONSTANT c_db_block_len : NATURAL := c_page_size;
-- Configuration of the block generator:
CONSTANT c_bg_nof_output_streams : POSITIVE := 1;
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*8;
CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
CONSTANT c_bg_data_file_prefix : STRING := "../../../src/hex/tb_bg_dat";
CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 1, 1);
-- Configuration of the databuffers:
CONSTANT c_db_nof_streams : POSITIVE := 1;
CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
CONSTANT c_db_data_type : t_diag_data_type_enum := e_data;
SIGNAL bg_siso_arr : t_dp_siso_arr(1 -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL bg_sosi_arr : t_dp_sosi_arr(1 -1 DOWNTO 0);
SIGNAL out_sosi_arr : t_dp_sosi_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL out_siso_arr : t_dp_siso_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- Siganls to connect the memory driver with the mm register interface
SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_rst : STD_LOGIC := '1';
SIGNAL ctlr_gen_clk : STD_LOGIC;
SIGNAL ctlr_gen_rst : STD_LOGIC;
SIGNAL ctlr_rdy : STD_LOGIC;
SIGNAL ctlr_init_done : STD_LOGIC;
SIGNAL dvr_start_addr : t_ddr3_addr;
SIGNAL dvr_end_addr : t_ddr3_addr;
SIGNAL dvr_en : STD_LOGIC;
SIGNAL dvr_wr_not_rd : STD_LOGIC;
SIGNAL dvr_done : STD_LOGIC;
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_ddr3_phy_in;
SIGNAL phy_io : t_ddr3_phy_io;
SIGNAL phy_ou : t_ddr3_phy_ou;
SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
ctlr_ref_clk <= NOT ctlr_ref_clk AFTER c_ctrl_ref_clk_period/2;
ctlr_rst <= '1', '0' AFTER c_ctrl_ref_clk_period*5;
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
----------------------------------------------------------------------------
-- MM buses
----------------------------------------------------------------------------
-- TB
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
u_mm_file_ram_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
u_bg : ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP(
g_nof_streams => c_bg_nof_output_streams,
g_buf_dat_w => c_bg_buf_dat_w,
g_buf_addr_w => c_bg_buf_adr_w,
g_file_index_arr => c_bg_data_file_index_arr,
g_file_name_prefix => c_bg_data_file_prefix
)
PORT MAP(
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
en_sync => dp_pps,
-- MM interface
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
ram_bg_data_mosi => ram_diag_bg_mosi,
ram_bg_data_miso => ram_diag_bg_miso,
-- ST interface
out_siso_arr => bg_siso_arr,
out_sosi_arr => bg_sosi_arr
);
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
u_dut: ENTITY work.seq_ddr3
GENERIC MAP(
g_ddr => c_ddr,
g_mts => c_mts,
g_phy => c_phy,
g_data_w => c_data_w,
g_ddr3_seq => c_ddr3_seq_conf
)
PORT MAP (
ctlr_ref_clk => ctlr_ref_clk,
ctlr_rst => ctlr_rst,
ctlr_gen_clk => open,
ctlr_gen_rst => open,
wr_clk => dp_clk,
wr_rst => dp_rst,
wr_sosi => bg_sosi_arr(0),
wr_siso => bg_siso_arr(0),
flush_ena => '0',
rd_sosi => out_sosi_arr(0),
rd_siso => out_siso_arr(0),
rd_clk => dp_clk,
rd_rst => dp_rst,
ddr3_in => phy_in,
ddr3_io => phy_io,
ddr3_ou => phy_ou
);
gen_u_800_model : IF c_phy > 0 GENERATE
u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
generic map (
MEM_IF_ADDR_WIDTH => 15,
MEM_IF_ROW_ADDR_WIDTH => 15,
MEM_IF_COL_ADDR_WIDTH => 10,
MEM_IF_CS_PER_RANK => 1,
MEM_IF_CONTROL_WIDTH => 1,
MEM_IF_DQS_WIDTH => 8,
MEM_IF_CS_WIDTH => 2,
MEM_IF_BANKADDR_WIDTH => 3,
MEM_IF_DQ_WIDTH => 64,
MEM_IF_CK_WIDTH => 2,
MEM_IF_CLK_EN_WIDTH => 2,
DEVICE_WIDTH => 1,
MEM_TRCD => 6,
MEM_TRTP => 3,
MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
MEM_IF_ODT_WIDTH => 2,
MEM_MIRROR_ADDRESSING_DEC => 0,
MEM_REGDIMM_ENABLED => false,
DEVICE_DEPTH => 1,
MEM_GUARANTEED_WRITE_INIT => false,
MEM_VERBOSE => true,
MEM_INIT_EN => false,
MEM_INIT_FILE => "",
DAT_DATA_WIDTH => 32
)
port map (
mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
mem_ba => phy_ou.ba,
mem_ck => phy_io.clk,
mem_ck_n => phy_io.clk_n,
mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
mem_dm => phy_ou.dm,
mem_ras_n => ras_n,
mem_cas_n => cas_n,
mem_we_n => we_n,
mem_reset_n => phy_ou.reset_n,
mem_dq => phy_io.dq,
mem_dqs => phy_io.dqs,
mem_dqs_n => phy_io.dqs_n,
mem_odt => phy_ou.odt
);
ras_n(0) <= phy_ou.ras_n;
cas_n(0) <= phy_ou.cas_n;
we_n(0) <= phy_ou.we_n;
END GENERATE;
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
u_data_buf : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
g_nof_streams => c_db_nof_streams,
g_data_type => c_db_data_type,
g_data_w => c_db_data_w,
g_buf_nof_data => c_db_buf_nof_data,
g_buf_use_sync => c_db_buf_use_sync
)
PORT MAP (
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- MM interface
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi,
reg_data_buf_miso => reg_diag_data_buf_miso,
-- ST interface
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
END tb;
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