Added missing r-6, r-9 items in tech_10gbase_r_component_pkg.vhd and ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl

This reverts commit ef19a04f, reversing
changes made to 4a55fb28.

. Completed data path from inputs to outputs through all stages.
Updated arts_unb2b_sc3 such that it compiles in Quartus.
. Commented out MMM due to QSYS IP issues
. Added IP for 3-channel 10GbE base-R (all mods in technology dir)
. Added g_direction generic to unb2b_board_10gbe in anticipation of
  having to split up the now duplex I/O to
  . the RX part in the input stage
  . the TX part in the output stage

drive 1xPHY or 1 ATXPLL will drive 12xPHY (recommented by Altera)

(MCGB) (x6/xN)

Use fractional PLL to created 156.25 MHz and 312.5 MHz for mac_10g and for 10gbase_r. The 10gbase_r XGMII interface is not available at 32b so need to stick to 64b@ 156.25MHz.

Added tb_tb_tb_eth.vhd to simulate eth for multiple technologies (currently only stratixiv).

Added regression tbfor eth library. Still need to fix run -all, because due to sim FAILURE the sim already stops at the first tb that finishes.

- Use common_network_layers_pkg from common (was eth_layers in $UNB)
- Use tech_tse_pkg and tb_tech_tse_pkg from tech_tse_lib (was work=tse_lib in $UNB)

Use ip_<device name> directories instead of following the altera/altera_mf library namings.
Move all Altera IP for Stratix IV to ip_stratixiv/ and use prefix ip_stratixiv_<component_name> for the IP files.
Remove xilinx/xilinx_core directory. Instead added ip_virtex4/ directory with empty hdllib.cfg.

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.