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Commit b948db5c authored by Daniel van der Schuur's avatar Daniel van der Schuur
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Updated arts_unb2b_sc3 such that it compiles in ModelSim. 

. Completed data path from inputs to outputs through all stages.
Updated arts_unb2b_sc3 such that it compiles in Quartus.
. Commented out MMM due to QSYS IP issues
. Added IP for 3-channel 10GbE base-R (all mods in technology dir)
. Added g_direction generic to unb2b_board_10gbe in anticipation of
  having to split up the now duplex I/O to
  . the RX part in the input stage
  . the TX part in the output stage
parent 547e97fe
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applications/arts/designs/arts_unb2b_sc3/hdllib.cfg
+ 13
− 5
View file @ b948db5c
hdl_lib_name = arts_unb2b_sc3
hdl_library_clause_name = arts_unb2b_sc3_lib
hdl_lib_uses_synth = common technology mm unb2b_board unb2b_board_10gbe dp eth tech_tse tr_10GbE diagnostics diag tech_mac_10g arts_unb1_sc4
hdl_lib_uses_synth = common technology mm unb2b_board unb2b_board_10gbe dp eth tech_tse tr_10GbE diagnostics diag tech_mac_10g arts_unb1_sc4 apertif arts_tab_beamformer iquv
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
hdl_lib_include_ip =
......@@ -11,12 +11,14 @@ hdl_lib_include_ip =
ip_arria10_e1sg_transceiver_pll_10g
ip_arria10_e1sg_phy_10gbase_r
ip_arria10_e1sg_phy_10gbase_r_3
ip_arria10_e1sg_phy_10gbase_r_4
ip_arria10_e1sg_phy_10gbase_r_12
ip_arria10_e1sg_phy_10gbase_r_24
ip_arria10_e1sg_phy_10gbase_r_48
ip_arria10_e1sg_transceiver_reset_controller_1
ip_arria10_e1sg_transceiver_reset_controller_3
ip_arria10_e1sg_transceiver_reset_controller_4
ip_arria10_e1sg_transceiver_reset_controller_12
ip_arria10_e1sg_transceiver_reset_controller_24
......@@ -25,13 +27,19 @@ hdl_lib_include_ip =
synth_files =
src/vhdl/qsys_arts_unb2b_sc3_pkg.vhd
src/vhdl/arts_unb2b_sc3_mm_master.vhd
# src/vhdl/arts_unb2b_sc3_input.vhd
# src/vhdl/arts_unb2b_sc3_processing.vhd
# src/vhdl/arts_unb2b_sc3_output.vhd
src/vhdl/arts_unb2b_sc3_input.vhd
src/vhdl/arts_unb2b_sc3_processing.vhd
# Workaround; we can't use unb1 libs in unb2b Questasim (yet).
$RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd
$RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
$RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_buffer.vhd
$RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_iquv_packetizer.vhd
$RADIOHDL/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab.vhd
src/vhdl/arts_unb2b_sc3_output.vhd
src/vhdl/arts_unb2b_sc3.vhd
test_bench_files =
tb/vhdl/tb_arts_unb2b_sc3.vhd
# tb/vhdl/tb_arts_unb2b_sc3.vhd
[modelsim_project_file]
......
applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_mm_master.vhd
+ 4
− 1
View file @ b948db5c
......@@ -130,7 +130,10 @@ ENTITY arts_unb2b_sc3_mm_master IS
reg_eth10g_qsfp_ring_mosi : OUT t_mem_mosi;
reg_eth10g_qsfp_ring_miso : IN t_mem_miso
reg_eth10g_qsfp_ring_miso : IN t_mem_miso;
reg_dp_bsn_align_mosi : OUT t_mem_mosi;
reg_dp_bsn_align_miso : IN t_mem_miso
);
END arts_unb2b_sc3_mm_master;
......
applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_output.vhd
+ 182
− 17
View file @ b948db5c
......@@ -28,12 +28,15 @@
-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
-- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
-- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
-- Output: iquv_src_out_arr
-- Output: src_out_arr
-- . TODO
-- Description:
-- . The CB set outputs 0.. 7 connect to QSFP_0_TX..QSFP_1_TX.
-- . FIXME arts_unb1_sc4_output_tab is using way too much MM address space
-- . too many header fields are MM controllable
-- . Why is MM control of IP, MAC duplicated?
-- Output: i_src_out_arr
LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib;
LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib, arts_unb1_sc4_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
......@@ -45,24 +48,186 @@ ENTITY arts_unb2b_sc3_output IS
GENERIC (
g_technology : NATURAL := c_tech_arria10_e1sg;
g_sim : BOOLEAN := FALSE;
g_nof_cbsets : NATURAL,
g_nof_cbsets : NATURAL;
g_nof_cb_per_set : NATURAL;
g_nof_subbands_per_cb : NATURAL;
g_nof_channels : NATURAL;
g_nof_timesamples : NATURAL;
g_nof_tabs : NATURAL;
g_iquv_data_w_out : NATURAL
);
PORT (
src_out_2arr : IN t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 9 TABs
iquv_src_out_arr : OUT t_dp_sosi_arr(g_nof_cb-1 DOWNTO 0); -- 40 CB
i_src_out_arr : OUT t_dp_sosi_arr(g_nof_cb-1 DOWNTO 0) -- 40 CB
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
snk_in_2arr_9 : IN t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 9 TABs
general_bsn_arr : IN t_slv_64_arr(g_nof_cbsets-1 DOWNTO 0);
src_out_arr : OUT t_dp_sosi_arr(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * I and IQUV interleaved
src_in_arr : IN t_dp_siso_arr(g_nof_cbsets-1 DOWNTO 0);
reg_dp_offload_tx_tab_iquv_hdr_dat_mosi : IN t_mem_mosi;
reg_dp_offload_tx_tab_iquv_hdr_dat_miso : OUT t_mem_miso;
reg_dp_xonoff_tab_iquv_mosi : IN t_mem_mosi;
reg_dp_xonoff_tab_iquv_miso : OUT t_mem_miso;
reg_dp_offload_tx_tab_i_hdr_dat_mosi : IN t_mem_mosi;
reg_dp_offload_tx_tab_i_hdr_dat_miso : OUT t_mem_miso;
reg_tab_dest_ip_mosi : IN t_mem_mosi;
reg_tab_dest_ip_miso : OUT t_mem_miso;
reg_tab_dest_mac_mosi : IN t_mem_mosi;
reg_tab_dest_mac_miso : OUT t_mem_miso;
reg_dp_xonoff_tab_i_mosi : IN t_mem_mosi;
reg_dp_xonoff_tab_i_miso : OUT t_mem_miso;
ID : IN STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0)
);
END arts_unb2b_sc3_output;
ARCHITECTURE str OF arts_unb2b_sc3_output IS
SIGNAL reg_dp_offload_tx_tab_iquv_hdr_dat_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_dp_offload_tx_tab_iquv_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_dp_xonoff_tab_iquv_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_dp_xonoff_tab_iquv_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_dp_offload_tx_tab_i_hdr_dat_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_dp_offload_tx_tab_i_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_tab_dest_ip_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_tab_dest_ip_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_tab_dest_mac_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_tab_dest_mac_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_dp_xonoff_tab_i_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL reg_dp_xonoff_tab_i_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL unb1_id : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
BEGIN
gen_arts_unb1_sc4_output_tab : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
-- u_arts_unb1_sc4_output_tab : ENTITY arts_unb1_sc4_lib.arts_unb1_sc4_output_tab --workaround, can't include unb1 libs in unb2b QuestaSim
u_arts_unb1_sc4_output_tab : ENTITY work.arts_unb1_sc4_output_tab
GENERIC MAP (
g_sim => g_sim,
g_override_payload_data => FALSE,
g_nof_tabs => g_nof_tabs,
g_nof_compound_beams => g_nof_cb_per_set,
g_nof_subbands_per_compound_beam => g_nof_subbands_per_cb,
g_nof_stokes => 4,
g_nof_channels => g_nof_channels,
g_nof_timesamples => g_nof_timesamples,
g_nof_bytes_per_iquv_packet => 8000,
g_nof_bytes_per_i_packet => 6250
)
PORT MAP (
dp_clk => dp_clk,
dp_rst => dp_rst,
mm_clk => mm_clk,
mm_rst => mm_rst,
general_bsn => general_bsn_arr(i),
tab_snk_in_arr => snk_in_2arr_9(i),
tab_src_out => src_out_arr(i),
tab_src_in => src_in_arr(i),
reg_dp_offload_tx_iquv_hdr_dat_mosi => reg_dp_offload_tx_tab_iquv_hdr_dat_mosi_arr(i),
reg_dp_offload_tx_iquv_hdr_dat_miso => reg_dp_offload_tx_tab_iquv_hdr_dat_miso_arr(i),
reg_dp_xonoff_iquv_mosi => reg_dp_xonoff_tab_iquv_mosi_arr(i),
reg_dp_xonoff_iquv_miso => reg_dp_xonoff_tab_iquv_miso_arr(i),
reg_dp_offload_tx_i_hdr_dat_mosi => reg_dp_offload_tx_tab_i_hdr_dat_mosi_arr(i),
reg_dp_offload_tx_i_hdr_dat_miso => reg_dp_offload_tx_tab_i_hdr_dat_miso_arr(i),
reg_tab_dest_ip_mosi => reg_tab_dest_ip_mosi_arr(i),
reg_tab_dest_ip_miso => reg_tab_dest_ip_miso_arr(i),
reg_tab_dest_mac_mosi => reg_tab_dest_mac_mosi_arr(i),
reg_tab_dest_mac_miso => reg_tab_dest_mac_miso_arr(i),
reg_dp_xonoff_i_mosi => reg_dp_xonoff_tab_i_mosi_arr(i),
reg_dp_xonoff_i_miso => reg_dp_xonoff_tab_i_miso_arr(i),
ID => unb1_id
);
-- Convert unb2 ID + CB set index to unb1 ID
-- . CB set index = unb1 chip ID
-- . unb2 backplane index && unb2 chip ID = unb1 backplane ID (band 0..15)
unb1_id <= ID(4 DOWNTO 0) & TO_UVEC(i, 3);
END GENERATE;
-- MM bus multiplexers
u_common_mem_mux_reg_dp_offload_tx_tab_iquv_hdr_dat : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_cbsets,
g_mult_addr_w => 6
)
PORT MAP (
mosi => reg_dp_offload_tx_tab_iquv_hdr_dat_mosi,
miso => reg_dp_offload_tx_tab_iquv_hdr_dat_miso,
mosi_arr => reg_dp_offload_tx_tab_iquv_hdr_dat_mosi_arr,
miso_arr => reg_dp_offload_tx_tab_iquv_hdr_dat_miso_arr
);
u_common_mem_mux_reg_dp_xonoff_tab_iquv : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_cbsets,
g_mult_addr_w => 1
)
PORT MAP (
mosi => reg_dp_xonoff_tab_iquv_mosi,
miso => reg_dp_xonoff_tab_iquv_miso,
mosi_arr => reg_dp_xonoff_tab_iquv_mosi_arr,
miso_arr => reg_dp_xonoff_tab_iquv_miso_arr
);
u_common_mem_mux_reg_dp_offload_tx_tab_i_hdr_dat : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_cbsets,
g_mult_addr_w => 9
)
PORT MAP (
mosi => reg_dp_offload_tx_tab_i_hdr_dat_mosi,
miso => reg_dp_offload_tx_tab_i_hdr_dat_miso,
mosi_arr => reg_dp_offload_tx_tab_i_hdr_dat_mosi_arr,
miso_arr => reg_dp_offload_tx_tab_i_hdr_dat_miso_arr
);
u_common_mem_mux_reg_tab_dest_ip : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_cbsets,
g_mult_addr_w => 3
)
PORT MAP (
mosi => reg_tab_dest_ip_mosi,
miso => reg_tab_dest_ip_miso,
mosi_arr => reg_tab_dest_ip_mosi_arr,
miso_arr => reg_tab_dest_ip_miso_arr
);
u_common_mem_mux_reg_tab_dest_mac : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_cbsets,
g_mult_addr_w => 4
)
PORT MAP (
mosi => reg_tab_dest_mac_mosi,
miso => reg_tab_dest_mac_miso,
mosi_arr => reg_tab_dest_mac_mosi_arr,
miso_arr => reg_tab_dest_mac_miso_arr
);
u_common_mem_mux_reg_dp_xonoff_tab_i : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_cbsets,
g_mult_addr_w => 1
)
PORT MAP (
mosi => reg_dp_xonoff_tab_i_mosi,
miso => reg_dp_xonoff_tab_i_miso,
mosi_arr => reg_dp_xonoff_tab_i_mosi_arr,
miso_arr => reg_dp_xonoff_tab_i_miso_arr
);
END str;
applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_processing.vhd
+ 65
− 24
View file @ b948db5c
......@@ -23,16 +23,16 @@
-- Authors:
-- . Daniel van der Schuur
-- Purpose: Create 9 TABs + integrated Stokes params for 40 Compound Beams
-- . Input: snk_in_2arr
-- . Input: snk_in_2arr_8
-- . [8 CB sets * 8 dishes] * [[5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits] / 1.024s]
-- (<--- 64 streams --->) * (<---------------- 187.5 Msps * 18b = 3.375 Gbps ------------------>)
-- (<-------------------------- 64 streams * 3.375 Gbps = 216 Gbps ---------------------------->)
-- . Output: src_out_2arr
-- . Output: src_out_2arr_9
-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
-- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
-- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib, arts_unb1_sc4_lib;
LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_board_10gbe_lib, dp_lib, tr_10GbE_lib, technology_lib, arts_unb1_sc4_lib, arts_tab_beamformer_lib, iquv_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
......@@ -51,18 +51,46 @@ ENTITY arts_unb2b_sc3_processing IS
g_nof_beamlets : NATURAL;
g_nof_tabs : NATURAL;
g_iquv_nof_int : NATURAL;
g_iquv_data_w_out : NATURAL;
g_iquv_data_w_out : NATURAL
);
PORT (
snk_in_2arr : IN t_dp_sosi_2arr_8(g_nof_cbsets-1 DOWNTO 0), -- 8 CB sets * 8 dishes
src_out_2arr : OUT t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0) -- 8 CB sets * 9 TABs
dp_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
snk_in_2arr_8 : IN t_dp_sosi_2arr_8(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 8 dishes
src_out_2arr_9 : OUT t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0); -- 8 CB sets * 9 TABs
ram_arts_tab_beamformer_mosi : IN t_mem_mosi;
ram_arts_tab_beamformer_miso : OUT t_mem_miso := c_mem_miso_rst
);
END arts_unb2b_sc3_processing;
ARCHITECTURE str OF arts_unb2b_sc3_processing IS
-------------------------------------------------------------------------------
-- arts_tab_beamformer
-------------------------------------------------------------------------------
SIGNAL arts_tab_beamformer_src_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
SIGNAL ram_arts_tab_beamformer_mosi_arr : t_mem_mosi_arr(g_nof_cbsets-1 DOWNTO 0);
SIGNAL ram_arts_tab_beamformer_miso_arr : t_mem_miso_arr(g_nof_cbsets-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- IQUV
-------------------------------------------------------------------------------
CONSTANT c_iquv_data_w_in : NATURAL := 2*g_data_w; --TAB BF output width --FIXME Do we really need 18b complex on 72 streams?
CONSTANT c_out_data_w_iquv : NATURAL := 8;
SIGNAL iquv_i_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
SIGNAL iquv_q_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
SIGNAL iquv_u_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
SIGNAL iquv_v_out_2arr_9 : t_dp_sosi_2arr_9(g_nof_cbsets-1 DOWNTO 0);
BEGIN
......@@ -70,11 +98,11 @@ BEGIN
-- arts_tab_beamformer (8x):
-- . Purpose:
-- . Create 9 TABs per CB
-- . Input: snk_in_2arr
-- . Input: snk_in_2arr_8
-- . [8 CB sets * 8 dishes] * [[5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits] / 1.024s]
-- (<--- 64 streams --->) * (<---------------- 187.5 Msps * 18b = 3.375 Gbps ------------------>)
-- (<-------------------------- 64 streams * 3.375 Gbps = 216 Gbps ---------------------------->)
-- . Output: arts_tab_beamformer_src_out_2arr
-- . Output: arts_tab_beamformer_src_out_2arr_9
-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][64 channels][2 pols][18 bits] / 1.024s]
-- (<-- 72 streams -->) * (<---------------- 187.5 Msps * 18b = 3.375 Gbps ------------------>)
-- (<-------------------------- 72 streams * 3.375 Gbps = 243 Gbps -------------------------->)
......@@ -99,23 +127,36 @@ BEGIN
ram_mosi => ram_arts_tab_beamformer_mosi_arr(i),
ram_miso => ram_arts_tab_beamformer_miso_arr(i),
snk_in_arr => snk_in_2arr(i),
src_out_arr => arts_tab_beamformer_src_out_2arr(i)
snk_in_arr => snk_in_2arr_8(i),
src_out_arr => arts_tab_beamformer_src_out_2arr_9(i)
);
END GENERATE;
-- MM bus multiplexer
u_common_mem_mux : ENTITY common_lib.common_mem_mux
GENERIC MAP (
g_nof_mosi => g_nof_cbsets,
g_mult_addr_w => ceil_log2(2*g_nof_beamlets)
)
PORT MAP (
mosi => ram_arts_tab_beamformer_mosi,
miso => ram_arts_tab_beamformer_miso,
mosi_arr => ram_arts_tab_beamformer_mosi_arr,
miso_arr => ram_arts_tab_beamformer_miso_arr
);
-------------------------------------------------------------------------------
-- IQUV
-- . Purpose:
-- . For each TAB, calculate IQUV + integrate 1/16
-- . Input: arts_tab_beamformer_src_out_2arr
-- . Output: src_out_2arr
-- . Input: arts_tab_beamformer_src_out_2arr_9
-- . Output: src_out_2arr_9
-- . [8 CB sets * 9 TABs] * [[5 CB][24 sb][12500 samples][4 channels][4*8 bits] / 1.024s]
-- (<-- 72 streams -->) * (<---------- 11.718750 Msps * 4*8b = 187.5 Mbps ----------->)
-- (<--------------------- 72 streams * 187.5 Mbps = 13.5 Gbps ---------------------->)
-------------------------------------------------------------------------------
gen_arts_tab_beamformer : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
gen_iquv : FOR j IN 0 TO g_nof_tabs-1 GENERATE
gen_iquv : FOR i IN 0 TO g_nof_cbsets-1 GENERATE
gen_j : FOR j IN 0 TO g_nof_tabs-1 GENERATE
u_iquv : ENTITY iquv_lib.iquv
GENERIC MAP (
g_sim => g_sim,
......@@ -128,19 +169,19 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
in_complex => arts_tab_beamformer_src_out_2arr(i)(j),
in_complex => arts_tab_beamformer_src_out_2arr_9(i)(j),
i_out => src_out_2arr(i)(j),
q_out => src_out_2arr(i)(j),
u_out => src_out_2arr(i)(j),
v_out => src_out_2arr(i)(j)
i_out => iquv_i_out_2arr_9(i)(j),
q_out => iquv_q_out_2arr_9(i)(j),
u_out => iquv_u_out_2arr_9(i)(j),
v_out => iquv_v_out_2arr_9(i)(j)
);
src_out_2arr(i)(j).valid <= iquv_iab_i_out.valid;
src_out_2arr(i)(j).data(4*c_out_data_w_iquv-1 downto 0) <= iquv_v_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0)
& iquv_u_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0)
& iquv_q_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0)
& iquv_i_out_arr(i)(j).data(c_out_data_w_iquv-1 downto 0);
src_out_2arr_9(i)(j).valid <= iquv_i_out_2arr_9(i)(0).valid;
src_out_2arr_9(i)(j).data(4*c_out_data_w_iquv-1 downto 0) <= iquv_v_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0)
& iquv_u_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0)
& iquv_q_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0)
& iquv_i_out_2arr_9(i)(j).data(c_out_data_w_iquv-1 downto 0);
END GENERATE;
END GENERATE;
......
boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+ 2
− 0
View file @ b948db5c
......@@ -34,6 +34,7 @@ ENTITY unb2_board_10gbe IS
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
g_technology : NATURAL := c_tech_arria10;
g_nof_macs : NATURAL;
g_direction : STRING := "TX_RX"; -- "TX_RX", "TX_ONLY", "RX_ONLY"
g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
g_rx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
......@@ -99,6 +100,7 @@ BEGIN
g_sim => g_sim,
g_sim_level => 1,
g_nof_macs => g_nof_macs,
g_direction => g_direction,
g_tx_fifo_fill => g_tx_fifo_fill,
g_tx_fifo_size => g_tx_fifo_size
)
......
libraries/technology/10gbase_r/hdllib.cfg
+ 5
− 0
View file @ b948db5c
......@@ -12,6 +12,9 @@ hdl_lib_uses_ip = ip_arria10_phy_10gbase_r ip_arria10_e3sge3_
ip_arria10_transceiver_reset_controller_12 ip_arria10_e3sge3_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12
ip_arria10_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24
ip_arria10_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e1sg_transceiver_reset_controller_48
ip_arria10_e1sg_phy_10gbase_r_3
ip_arria10_e1sg_transceiver_reset_controller_3
hdl_lib_uses_sim =
hdl_lib_technology =
hdl_lib_disclose_library_clause_names =
......@@ -38,12 +41,14 @@ hdl_lib_disclose_library_clause_names =
ip_arria10_e3sge3_transceiver_reset_controller_24 ip_arria10_e3sge3_transceiver_reset_controller_24_altera_xcvr_reset_control_151
ip_arria10_e3sge3_transceiver_reset_controller_48 ip_arria10_e3sge3_transceiver_reset_controller_48_altera_xcvr_reset_control_151
ip_arria10_e1sg_phy_10gbase_r ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
ip_arria10_e1sg_phy_10gbase_r_3 ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_4 ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_12 ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_24 ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170
ip_arria10_e1sg_phy_10gbase_r_48 ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_170
ip_arria10_e1sg_transceiver_pll_10g ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_170
ip_arria10_e1sg_transceiver_reset_controller_1 ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_170
ip_arria10_e1sg_transceiver_reset_controller_3 ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
ip_arria10_e1sg_transceiver_reset_controller_4 ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_170
ip_arria10_e1sg_transceiver_reset_controller_12 ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_170
ip_arria10_e1sg_transceiver_reset_controller_24 ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_170
......
libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+ 81
− 1
View file @ b948db5c
......@@ -22,6 +22,7 @@
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_170;
LIBRARY ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170;
LIBRARY ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_170;
LIBRARY ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_170;
LIBRARY ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_170;
......@@ -214,7 +215,86 @@ BEGIN
END GENERATE;
END GENERATE;
gen_phy_3 : IF c_nof_channels_per_ip=3 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
tr_coreclkin_slv <= (OTHERS=>tr_coreclkin(0));
gen_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
tx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w) <= tx_parallel_data_arr(I);
tx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes) <= tx_control_arr(I);
rx_parallel_data_arr(I) <= rx_parallel_data_arr_slv((I+1)*c_xgmii_data_w-1 DOWNTO I*c_xgmii_data_w);
rx_control_arr(I) <= rx_control_arr_slv((I+1)*c_xgmii_nof_lanes-1 DOWNTO I*c_xgmii_nof_lanes);
END GENERATE;
u_ip_arria10_e1sg_phy_10gbase_r_3 : ip_arria10_e1sg_phy_10gbase_r_3
PORT MAP (
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy => tx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 => tx_serial_clk_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_serial_clk0.clk
rx_cdr_refclk0 => tr_ref_clk_644, -- in std_logic := '0'; -- rx_cdr_refclk0.clk
tx_serial_data => tx_serial_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- tx_serial_data.tx_serial_data
rx_serial_data => rx_serial_arr(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
--rx_is_lockedtoref : out std_logic_vector(11 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- out std_logic_vector(11 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
tx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- tx_coreclkin.clk
rx_coreclkin => tr_coreclkin_slv(IP_SIZE-1 DOWNTO 0), -- in std_logic_vector(11 downto 0) := (others => '0'); -- rx_coreclkin.clk
tx_parallel_data => tx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- in std_logic_vector(1535 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
rx_parallel_data => rx_parallel_data_arr_slv(IP_SIZE_DATA-1 DOWNTO 0), -- out std_logic_vector(1535 downto 0); -- rx_parallel_data.rx_parallel_data
tx_control => tx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0), -- in std_logic_vector(191 downto 0) := (others => '0'); -- tx_control.tx_control
rx_control => rx_control_arr_slv(IP_SIZE_CONTROL-1 DOWNTO 0) -- out std_logic_vector(191 downto 0); -- rx_control.rx_control
--tx_clkout : out std_logic_vector(11 downto 0); -- tx_clkout.clk
--rx_clkout : out std_logic_vector(11 downto 0); -- rx_clkout.clk
--tx_err_ins : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_err_ins.tx_err_ins
--tx_enh_data_valid : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
--tx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
--tx_enh_fifo_full : out std_logic_vector(11 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
--tx_enh_fifo_pempty : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
--tx_enh_fifo_pfull : out std_logic_vector(11 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
--tx_pma_div_clkout : out std_logic_vector(11 downto 0); -- tx_pma_div_clkout.clk
--rx_enh_blk_lock : out std_logic_vector(11 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
--rx_enh_data_valid : out std_logic_vector(11 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
--rx_enh_fifo_del : out std_logic_vector(11 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
--rx_enh_fifo_empty : out std_logic_vector(11 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
--rx_enh_fifo_full : out std_logic_vector(11 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
--rx_enh_fifo_insert : out std_logic_vector(11 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
--rx_enh_highber : out std_logic_vector(11 downto 0); -- rx_enh_highber.rx_enh_highber
--unused_rx_control : out std_logic_vector(287 downto 0); -- unused_rx_control.unused_rx_control
--unused_rx_parallel_data : out std_logic_vector(1535 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
--unused_tx_control : in std_logic_vector(215 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
--unused_tx_parallel_data : in std_logic_vector(1535 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
);
u_ip_arria10_e1sg_transceiver_reset_controller_3 : ip_arria10_e1sg_transceiver_reset_controller_3
PORT MAP (
clock => clk_156, -- : in std_logic := '0'; -- clock.clk
pll_locked => atx_pll_locked_arr(0 DOWNTO 0), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_powerdown => atx_pll_powerdown_arr(0 DOWNTO 0), -- : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
pll_select => "0", -- : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
reset => rst_156, -- : in std_logic := '0'; -- reset.reset
rx_analogreset => rx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_analogreset.rx_analogreset
rx_cal_busy => rx_cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_cal_busy.rx_cal_busy
rx_digitalreset => rx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_digitalreset.rx_digitalreset
rx_is_lockedtodata => rx_is_lockedtodata_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => xgmii_rx_ready_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- rx_ready.rx_ready
tx_analogreset => tx_analogreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_analogreset.tx_analogreset
tx_cal_busy => cal_busy_arr(IP_SIZE-1 DOWNTO 0), -- : in std_logic_vector(11 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
tx_digitalreset => tx_digitalreset_arr(IP_SIZE-1 DOWNTO 0), -- : out std_logic_vector(11 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready => xgmii_tx_ready_arr(IP_SIZE-1 DOWNTO 0) -- : out std_logic_vector(11 downto 0) -- tx_ready.tx_ready
);
END GENERATE;
gen_phy_4 : IF c_nof_channels_per_ip=4 GENERATE
tx_serial_clk_slv <= (OTHERS=>tx_serial_clk(0));
......
libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+ 74
− 0
View file @ b948db5c
......@@ -844,6 +844,61 @@ PACKAGE tech_10gbase_r_component_pkg IS
);
END COMPONENT;
component ip_arria10_e1sg_phy_10gbase_r_3 is
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
rx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(2 downto 0); -- rx_cal_busy
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
rx_clkout : out std_logic_vector(2 downto 0); -- clk
rx_control : out std_logic_vector(23 downto 0); -- rx_control
rx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
rx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(2 downto 0); -- rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(2 downto 0); -- rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(2 downto 0); -- rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(2 downto 0); -- rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(2 downto 0); -- rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(2 downto 0); -- rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(2 downto 0); -- rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(2 downto 0); -- rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(191 downto 0); -- rx_parallel_data
rx_prbs_done : out std_logic_vector(2 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(2 downto 0); -- rx_prbs_err
rx_prbs_err_clr : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_prbs_err_clr
rx_serial_data : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_serial_data
rx_seriallpbken : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_seriallpbken
tx_analogreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(2 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(2 downto 0); -- clk
tx_control : in std_logic_vector(23 downto 0) := (others => 'X'); -- tx_control
tx_coreclkin : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
tx_digitalreset : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_digitalreset
tx_enh_data_valid : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(2 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(2 downto 0); -- tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_err_ins
tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X'); -- tx_parallel_data
tx_serial_clk0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(2 downto 0); -- tx_serial_data
unused_rx_control : out std_logic_vector(35 downto 0); -- unused_rx_control
unused_rx_parallel_data : out std_logic_vector(191 downto 0); -- unused_rx_parallel_data
unused_tx_control : in std_logic_vector(26 downto 0) := (others => 'X'); -- unused_tx_control
unused_tx_parallel_data : in std_logic_vector(191 downto 0) := (others => 'X') -- unused_tx_parallel_data
);
end component ip_arria10_e1sg_phy_10gbase_r_3;
COMPONENT ip_arria10_e1sg_phy_10gbase_r_4
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
......@@ -1105,6 +1160,25 @@ PACKAGE tech_10gbase_r_component_pkg IS
);
END COMPONENT;
component ip_arria10_e1sg_transceiver_reset_controller_3 is
port (
clock : in std_logic := 'X'; -- clk
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
reset : in std_logic := 'X'; -- reset
rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
);
end component ip_arria10_e1sg_transceiver_reset_controller_3;
COMPONENT ip_arria10_e1sg_transceiver_reset_controller_4
port (
clock : in std_logic := '0'; -- clock.clk
......
libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl 0 → 100644
+ 35
− 0
View file @ b948db5c
#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generate_ip.sh 0 → 100755
+ 44
− 0
View file @ b948db5c
#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_e1sg_phy_10gbase_r_3.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg 0 → 100644
+ 19
− 0
View file @ b948db5c
hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_3
hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_170
hdl_lib_uses_synth =
hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_native_a10_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_phy_10gbase_r_3.qip
libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl 0 → 100644
+ 34
− 0
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#------------------------------------------------------------------------------
#
# Copyright (C) 2017
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on generated file mentor/msim_setup.tcl.
# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generated/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/generate_ip.sh 0 → 100755
+ 44
− 0
View file @ b948db5c
#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_e1sg_transceiver_reset_controller_3.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg 0 → 100644
+ 19
− 0
View file @ b948db5c
hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_3
hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_3_altera_xcvr_reset_control_170
hdl_lib_uses_synth =
hdl_lib_uses_sim = ip_arria10_e1sg_altera_xcvr_reset_control_170
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_transceiver_reset_controller_3.qip
libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qsys 0 → 100644
+ 175
− 0
View file @ b948db5c
<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e1sg_transceiver_reset_controller_3">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="INTERNAL_COMPONENT=true"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element transceiver_reset_controller_inst
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10AX115U2F45E1SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="clock"
internal="transceiver_reset_controller_inst.clock"
type="clock"
dir="end">
<port name="clock" internal="clock" />
</interface>
<interface
name="pll_locked"
internal="transceiver_reset_controller_inst.pll_locked"
type="conduit"
dir="end">
<port name="pll_locked" internal="pll_locked" />
</interface>
<interface
name="pll_powerdown"
internal="transceiver_reset_controller_inst.pll_powerdown"
type="conduit"
dir="end">
<port name="pll_powerdown" internal="pll_powerdown" />
</interface>
<interface
name="pll_select"
internal="transceiver_reset_controller_inst.pll_select"
type="conduit"
dir="end">
<port name="pll_select" internal="pll_select" />
</interface>
<interface
name="reset"
internal="transceiver_reset_controller_inst.reset"
type="reset"
dir="end">
<port name="reset" internal="reset" />
</interface>
<interface
name="rx_analogreset"
internal="transceiver_reset_controller_inst.rx_analogreset"
type="conduit"
dir="end">
<port name="rx_analogreset" internal="rx_analogreset" />
</interface>
<interface
name="rx_cal_busy"
internal="transceiver_reset_controller_inst.rx_cal_busy"
type="conduit"
dir="end">
<port name="rx_cal_busy" internal="rx_cal_busy" />
</interface>
<interface
name="rx_digitalreset"
internal="transceiver_reset_controller_inst.rx_digitalreset"
type="conduit"
dir="end">
<port name="rx_digitalreset" internal="rx_digitalreset" />
</interface>
<interface
name="rx_is_lockedtodata"
internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
type="conduit"
dir="end">
<port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
</interface>
<interface
name="rx_ready"
internal="transceiver_reset_controller_inst.rx_ready"
type="conduit"
dir="end">
<port name="rx_ready" internal="rx_ready" />
</interface>
<interface
name="tx_analogreset"
internal="transceiver_reset_controller_inst.tx_analogreset"
type="conduit"
dir="end">
<port name="tx_analogreset" internal="tx_analogreset" />
</interface>
<interface
name="tx_cal_busy"
internal="transceiver_reset_controller_inst.tx_cal_busy"
type="conduit"
dir="end">
<port name="tx_cal_busy" internal="tx_cal_busy" />
</interface>
<interface
name="tx_digitalreset"
internal="transceiver_reset_controller_inst.tx_digitalreset"
type="conduit"
dir="end">
<port name="tx_digitalreset" internal="tx_digitalreset" />
</interface>
<interface
name="tx_ready"
internal="transceiver_reset_controller_inst.tx_ready"
type="conduit"
dir="end">
<port name="tx_ready" internal="tx_ready" />
</interface>
<module
name="transceiver_reset_controller_inst"
kind="altera_xcvr_reset_control"
version="17.0"
enabled="1"
autoexport="1">
<parameter name="CHANNELS" value="3" />
<parameter name="PLLS" value="1" />
<parameter name="REDUCED_SIM_TIME" value="1" />
<parameter name="RX_ENABLE" value="1" />
<parameter name="RX_PER_CHANNEL" value="1" />
<parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
<parameter name="SYNCHRONIZE_RESET" value="1" />
<parameter name="SYS_CLK_IN_MHZ" value="156" />
<parameter name="TX_ENABLE" value="1" />
<parameter name="TX_PER_CHANNEL" value="0" />
<parameter name="TX_PLL_ENABLE" value="1" />
<parameter name="T_PLL_LOCK_HYST" value="60" />
<parameter name="T_PLL_POWERDOWN" value="1000" />
<parameter name="T_RX_ANALOGRESET" value="70000" />
<parameter name="T_RX_DIGITALRESET" value="4000" />
<parameter name="T_TX_ANALOGRESET" value="70000" />
<parameter name="T_TX_DIGITALRESET" value="70000" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_pll_cal_busy" value="0" />
<parameter name="gui_rx_auto_reset" value="0" />
<parameter name="gui_split_interfaces" value="0" />
<parameter name="gui_tx_auto_reset" value="0" />
</module>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
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