No need to use ip/ and no need to use *_top.vhd. Directly use generated *.vhd component.

libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd

@@ -107,7 +107,7 @@ BEGIN
   
     xgmii_rx_dc_arr(I)      <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
   
-    u_ip_arria10_phy_10gbase_r_top : ip_arria10_phy_10gbase_r_top
+    u_ip_arria10_phy_10gbase_r : ip_arria10_phy_10gbase_r
     PORT MAP (
       tx_analogreset          => tx_analogreset_arr(I DOWNTO I),
       tx_digitalreset         => tx_digitalreset_arr(I DOWNTO I),
@@ -153,7 +153,7 @@ BEGIN
       --rx_enh_blk_lock         : out std_logic_vector(0 downto 0);                     --         rx_enh_blk_lock.rx_enh_blk_lock
     );
   
-    u_ip_arria10_transceiver_reset_controller_1_top : ip_arria10_transceiver_reset_controller_1_top
+    u_ip_arria10_transceiver_reset_controller_1 : ip_arria10_transceiver_reset_controller_1
     PORT MAP (
       clock              => clk_156,
       reset              => rst_156,
@@ -173,7 +173,7 @@ BEGIN
   END GENERATE;
 
   -- ATX PLL
-  u_ip_arria10_transceiver_pll_10g_top : ip_arria10_transceiver_pll_10g_top
+  u_ip_arria10_transceiver_pll_10g : ip_arria10_transceiver_pll_10g
   PORT MAP (
     pll_powerdown => atx_pll_powerdown(0),
     pll_refclk0   => tr_ref_clk_644,

libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd

@@ -31,8 +31,7 @@ PACKAGE tech_10gbase_r_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd
-  COMPONENT ip_arria10_phy_10gbase_r_top IS
+  COMPONENT ip_arria10_phy_10gbase_r IS
   PORT (
     tx_analogreset          : in  std_logic_vector(0 downto 0)  := (others => '0'); --          tx_analogreset.tx_analogreset
     tx_digitalreset         : in  std_logic_vector(0 downto 0)  := (others => '0'); --         tx_digitalreset.tx_digitalreset
@@ -75,8 +74,7 @@ PACKAGE tech_10gbase_r_component_pkg IS
   );
   END COMPONENT;
 
-  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
-  COMPONENT ip_arria10_transceiver_pll_10g_top IS
+  COMPONENT ip_arria10_transceiver_pll_10g IS
   PORT (
     pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
     pll_refclk0   : in  std_logic := '0'; --   pll_refclk0.clk
@@ -86,8 +84,7 @@ PACKAGE tech_10gbase_r_component_pkg IS
   );
   END COMPONENT;
 
-  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1_top.vhd
-  COMPONENT ip_arria10_transceiver_reset_controller_1_top IS
+  COMPONENT ip_arria10_transceiver_reset_controller_1 IS
   PORT (
     clock              : in  std_logic                    := '0';             --              clock.clk
     reset              : in  std_logic                    := '0';             --              reset.reset

libraries/technology/mac_10g/tech_mac_10g_arria10.vhd

@@ -86,7 +86,7 @@ BEGIN
     rx_src_out.sop <= avalon_rx_src_out.sop AND avalon_rx_src_out.valid;
   END PROCESS;
   
-  u_ip_mac_10g : ip_arria10_mac_10g_top
+  u_ip_arria10_mac_10g : ip_arria10_mac_10g
   PORT MAP (
     csr_clk                         => mm_clk,
     csr_rst_n                       => mm_rst_n,

libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd

@@ -95,8 +95,7 @@ PACKAGE tech_mac_10g_component_pkg IS
   -- ip_arria10
   ------------------------------------------------------------------------------
   
-  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/mac_10g/ip/generated/sim/ip_arria10_mac_10g.vhd
-  COMPONENT ip_arria10_mac_10g_top IS
+  COMPONENT ip_arria10_mac_10g IS
   PORT (
     csr_read                        : in  std_logic                     := '0';             --                        csr.read
     csr_write                       : in  std_logic                     := '0';             --                           .write