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Commit d384ccbb authored by Eric Kooistra's avatar Eric Kooistra
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Added technology select support to test benches. 

Added tb_tb_tb_eth.vhd to simulate eth for multiple technologies (currently only stratixiv).
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libraries/io/eth/hdllib.cfg
+ 1
− 0
View file @ d384ccbb
......@@ -29,6 +29,7 @@ test_bench_files =
$UNB/Firmware/modules/tse/tb/vhdl/tb_eth_hdr.vhd
tb/vhdl/tb_eth.vhd
tb/vhdl/tb_tb_eth.vhd
tb/vhdl/tb_tb_tb_eth.vhd
tb/vhdl/tb_eth_udp_offload.vhd
tb/vhdl/tb_eth_ihl_to_20.vhd
tb/vhdl/tb_tb_tb_eth_regression.vhd
libraries/io/eth/tb/vhdl/tb_eth.vhd
+ 11
− 5
View file @ d384ccbb
......@@ -40,7 +40,7 @@
-- > run -all
LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib;
LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -49,14 +49,17 @@ USE common_lib.tb_common_mem_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE WORK.eth_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE WORK.eth_pkg.ALL;
ENTITY tb_eth IS
-- Test bench control parameters
GENERIC (
g_technology_dut : NATURAL := c_tech_stratixiv;
g_technology_lcu : NATURAL := c_tech_stratixiv;
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
-- g_data_type = c_tb_tech_tse_data_type_arp = 2
......@@ -298,7 +301,8 @@ BEGIN
-- Wait for ETH init
WHILE dut_eth_init='1' LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
-- Setup the TSE MAC
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(g_technology_dut,
c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_dut_src_mac, eth_psc_access,
mm_clk, eth_tse_miso, eth_tse_mosi);
dut_tse_init <= '0';
......@@ -399,7 +403,8 @@ BEGIN
-- Wait for reset release
WHILE mm_rst='1' LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
-- Setup the LCU TSE MAC
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(g_technology_lcu,
c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_lcu_src_mac, lcu_psc_access,
mm_clk, lcu_tse_miso, lcu_tse_mosi);
-- Wait for DUT init done
......@@ -476,6 +481,7 @@ BEGIN
dut : ENTITY work.eth
GENERIC MAP (
g_technology => g_technology_dut,
g_cross_clock_domain => c_cross_clock_domain
)
PORT MAP (
......@@ -560,7 +566,7 @@ BEGIN
REPORT "Not all transmitted packets were received." SEVERITY ERROR;
END IF;
WAIT FOR 10 us;
--WAIT FOR 10 us;
ASSERT FALSE REPORT "Simulation tb_eth finished." SEVERITY NOTE;
WAIT;
END PROCESS;
......
libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+ 6
− 2
View file @ d384ccbb
......@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib;
LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
......@@ -33,6 +33,7 @@ USE common_lib.common_network_total_header_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE WORK.eth_pkg.ALL;
......@@ -52,6 +53,7 @@ ARCHITECTURE tb OF tb_eth_udp_offload IS
CONSTANT c_rl : NATURAL := 1;
CONSTANT c_pulse_active : NATURAL := 1;
CONSTANT c_pulse_period : NATURAL := 7;
CONSTANT c_technology_dut : NATURAL := c_tech_stratixiv;
-- tb specific
CONSTANT c_nof_repeat : NATURAL := 10;
......@@ -258,7 +260,8 @@ BEGIN
-- Wait for ETH init
WHILE dut_eth_init='1' LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
-- Setup the TSE MAC
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(c_technology_dut,
c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_dut_src_mac, eth_psc_access,
mm_clk, eth_tse_miso, eth_tse_mosi);
dut_tse_init <= '0';
......@@ -384,6 +387,7 @@ BEGIN
------------------------------------------------------------------------------
dut : ENTITY work.eth
GENERIC MAP (
g_technology => c_technology_dut,
g_cross_clock_domain => TRUE
)
PORT MAP (
......
libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+ 13
− 7
View file @ d384ccbb
......@@ -27,25 +27,31 @@
-- > as 3
-- > run -all
LIBRARY IEEE, tech_tse_lib;
LIBRARY IEEE, technology_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE WORK.eth_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
ENTITY tb_tb_eth IS
GENERIC (
g_technology_dut : NATURAL := c_tech_stratixiv
);
END tb_tb_eth;
ARCHITECTURE tb OF tb_tb_eth IS
CONSTANT c_technology_lcu : NATURAL := c_tech_stratixiv;
BEGIN
-- Try ETH settings : GENERIC MAP (g_data_type => )
u_use_symbols : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_symbols);
u_use_counter : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_counter);
u_use_arp : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_arp );
u_use_ping : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_ping );
u_use_udp : ENTITY work.tb_eth GENERIC MAP (c_tb_tech_tse_data_type_udp );
u_use_symbols : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_symbols);
u_use_counter : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_counter);
u_use_arp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_arp );
u_use_ping : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_ping );
u_use_udp : ENTITY work.tb_eth GENERIC MAP (g_technology_dut, c_technology_lcu, c_tb_tech_tse_data_type_udp );
END tb;
libraries/io/eth/tb/vhdl/tb_tb_tb_eth.vhd 0 → 100644
+ 46
− 0
View file @ d384ccbb
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Multi-testbench for eth
-- Description:
-- Verify eth for different technologies
-- Usage:
-- > as 3
-- > run -all
LIBRARY IEEE, technology_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE WORK.eth_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
ENTITY tb_tb_tb_eth IS
END tb_tb_tb_eth;
ARCHITECTURE tb OF tb_tb_tb_eth IS
BEGIN
u_dut_stratixiv : ENTITY work.tb_tb_eth GENERIC MAP (c_tech_stratixiv);
END tb;
libraries/io/eth/tb/vhdl/tb_tb_tb_eth_regression.vhd
+ 1
− 1
View file @ d384ccbb
......@@ -35,7 +35,7 @@ END tb_tb_tb_eth_regression;
ARCHITECTURE tb OF tb_tb_tb_eth_regression IS
BEGIN
u_tb_tb_eth : ENTITY work.tb_tb_eth;
u_tb_tb_tb_eth : ENTITY work.tb_tb_tb_eth;
u_tb_eth_hdr : ENTITY work.tb_eth_hdr;
u_tb_eth_checksum : ENTITY work.tb_eth_checksum;
u_tb_eth_crc_ctrl : ENTITY work.tb_eth_crc_ctrl;
......
libraries/technology/tse/tb_tech_tse.vhd
+ 7
− 5
View file @ d384ccbb
......@@ -31,12 +31,12 @@
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE WORK.tech_tse_pkg.ALL;
USE WORK.tb_tech_tse_pkg.ALL;
......@@ -44,9 +44,10 @@ USE WORK.tb_tech_tse_pkg.ALL;
ENTITY tb_tech_tse IS
-- Test bench control parameters
GENERIC (
g_technology : NATURAL := c_tech_stratixiv;
-- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- g_data_type = c_tb_tech_tse_data_type_counter = 1
g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols
g_data_type : NATURAL := c_tb_tech_tse_data_type_symbols
);
END tb_tech_tse;
......@@ -143,7 +144,8 @@ BEGIN
mm_rst <= '0';
FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
proc_tech_tse_setup(c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
proc_tech_tse_setup(g_technology,
c_promis_en, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tx_ready_latency,
c_src_mac, mm_psc_access,
mm_clk, mm_miso, mm_mosi);
mm_init <= '0';
......@@ -224,7 +226,7 @@ BEGIN
dut : ENTITY work.tech_tse
GENERIC MAP (
g_technology => c_tech_stratixiv,
g_technology => g_technology,
g_ETH_PHY => "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
)
PORT MAP (
......
libraries/technology/tse/tb_tech_tse_pkg.vhd
+ 36
− 7
View file @ d384ccbb
......@@ -20,16 +20,17 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, dp_lib;
LIBRARY IEEE, technology_lib, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
USE common_lib.common_network_layers_pkg.ALL;
USE common_lib.common_network_total_header_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE dp_lib.tb_dp_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE WORK.tech_tse_pkg.ALL;
......@@ -45,7 +46,8 @@ PACKAGE tb_tech_tse_pkg IS
FUNCTION func_tech_tse_header_size(data_type : NATURAL) RETURN NATURAL; -- raw ethernet: 4 header words, protocol ethernet: 11 header words
-- Configure the TSE MAC
PROCEDURE proc_tech_tse_setup(CONSTANT c_promis_en : IN BOOLEAN;
PROCEDURE proc_tech_tse_setup(CONSTANT c_technology : IN NATURAL;
CONSTANT c_promis_en : IN BOOLEAN;
CONSTANT c_tse_tx_fifo_depth : IN NATURAL;
CONSTANT c_tse_rx_fifo_depth : IN NATURAL;
CONSTANT c_tx_ready_latency : IN NATURAL;
......@@ -55,6 +57,16 @@ PACKAGE tb_tech_tse_pkg IS
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi);
PROCEDURE proc_tech_tse_setup_stratixiv(CONSTANT c_promis_en : IN BOOLEAN;
CONSTANT c_tse_tx_fifo_depth : IN NATURAL;
CONSTANT c_tse_rx_fifo_depth : IN NATURAL;
CONSTANT c_tx_ready_latency : IN NATURAL;
CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
SIGNAL psc_access : OUT STD_LOGIC;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi);
PROCEDURE proc_tech_tse_tx_packet(CONSTANT total_header : IN t_network_total_header;
CONSTANT data_len : IN NATURAL; -- in symbols = octets = bytes
CONSTANT c_data_type : IN NATURAL; -- c_tb_tech_tse_data_type_*
......@@ -108,8 +120,8 @@ PACKAGE BODY tb_tech_tse_pkg IS
-- Configure the TSE MAC
-- . The src_mac[47:0] = 0x123456789ABC for MAC address 12-34-56-78-9A-BC
PROCEDURE proc_tech_tse_setup(CONSTANT c_promis_en : IN BOOLEAN;
PROCEDURE proc_tech_tse_setup(CONSTANT c_technology : IN NATURAL;
CONSTANT c_promis_en : IN BOOLEAN;
CONSTANT c_tse_tx_fifo_depth : IN NATURAL;
CONSTANT c_tse_rx_fifo_depth : IN NATURAL;
CONSTANT c_tx_ready_latency : IN NATURAL;
......@@ -118,6 +130,23 @@ PACKAGE BODY tb_tech_tse_pkg IS
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi) IS
BEGIN
CASE c_technology IS
WHEN c_tech_stratixiv => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi);
WHEN OTHERS => proc_tech_tse_setup_stratixiv(c_promis_en, c_tse_tx_fifo_depth, c_tse_rx_fifo_depth, c_tx_ready_latency, src_mac, psc_access, mm_clk, mm_miso, mm_mosi); -- default to c_tech_stratixiv
END CASE;
END proc_tech_tse_setup;
-- . The src_mac[47:0] = 0x123456789ABC for MAC address 12-34-56-78-9A-BC
PROCEDURE proc_tech_tse_setup_stratixiv(CONSTANT c_promis_en : IN BOOLEAN;
CONSTANT c_tse_tx_fifo_depth : IN NATURAL;
CONSTANT c_tse_rx_fifo_depth : IN NATURAL;
CONSTANT c_tx_ready_latency : IN NATURAL;
CONSTANT src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE);
SIGNAL psc_access : OUT STD_LOGIC;
SIGNAL mm_clk : IN STD_LOGIC;
SIGNAL mm_miso : IN t_mem_miso;
SIGNAL mm_mosi : OUT t_mem_mosi) IS
CONSTANT c_mac0 : INTEGER := TO_SINT(hton(src_mac(47 DOWNTO 16), 4));
CONSTANT c_mac1 : INTEGER := TO_SINT(hton(src_mac(15 DOWNTO 0), 2));
BEGIN
......@@ -207,7 +236,7 @@ PACKAGE BODY tb_tech_tse_pkg IS
proc_mem_mm_bus_rd(16#0EC#, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
WAIT UNTIL rising_edge(mm_clk);
END proc_tech_tse_setup;
END proc_tech_tse_setup_stratixiv;
-- Transmit user packet
......
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