Added missing r-6, r-9 items in tech_10gbase_r_component_pkg.vhd and ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl

This reverts commit ef19a04f, reversing
changes made to 4a55fb28.

Bug fixes for e2sg IP

. Completed data path from inputs to outputs through all stages.
Updated arts_unb2b_sc3 such that it compiles in Quartus.
. Commented out MMM due to QSYS IP issues
. Added IP for 3-channel 10GbE base-R (all mods in technology dir)
. Added g_direction generic to unb2b_board_10gbe in anticipation of
  having to split up the now duplex I/O to
  . the RX part in the input stage
  . the TX part in the output stage

use the correct library names in the .../technology/ip_arria10_e1sg
folder

Use p_dummy process to avoid reaching report failure when running tb for unb1 which has no 10gbase_r.

Added regression_test_vhdl key, with tb_tech_10gbase_r.vhd that is not self checking yet and not applicable to unb1.

drive 1xPHY or 1 ATXPLL will drive 12xPHY (recommented by Altera)