Ported tse/eth* in $UNB to io/eth/ in $RADIOHDL.

- Use common_network_layers_pkg from common (was eth_layers in $UNB)
- Use tech_tse_pkg and tb_tech_tse_pkg from tech_tse_lib (was work=tse_lib in $UNB)

libraries/io/eth/hdllib.cfg

+hdl_lib_name = eth
+hdl_library_clause_name = eth_lib
+hdl_lib_uses = dp common tech_tse
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    src/vhdl/eth_pkg.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_checksum.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_hdr_store.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_hdr_status.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_hdr_ctrl.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_hdr.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_crc_ctrl.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_crc_word.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_mm_registers.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_mm_reg_frame.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_udp_channel.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_buffer.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_control.vhd
+    $UNB/Firmware/modules/tse/src/vhdl/eth_ihl_to_20.vhd
+    src/vhdl/eth.vhd
+    
+    src/vhdl/avs_eth.vhd
+    src/vhdl/avs_eth_coe.vhd
+    
+test_bench_files = 
+    $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_checksum.vhd
+    $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_crc_ctrl.vhd
+    $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_hdr.vhd
+    tb/vhdl/tb_eth.vhd
+    tb/vhdl/tb_tb_eth.vhd
+    tb/vhdl/tb_eth_udp_offload.vhd
+    $UNB/Firmware/modules/tse/tb/vhdl/tb_eth_ihl_to_20.vhd

libraries/io/eth/src/vhdl/avs_eth.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, tech_tse_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE work.eth_pkg.ALL;
+
+
+ENTITY avs_eth IS
+  PORT (
+    ---------------------------------------------------------------------------
+    -- Clock interface
+    ---------------------------------------------------------------------------
+    csi_mm_reset            : IN STD_LOGIC;
+    csi_mm_clk              : IN STD_LOGIC;
+    
+    ---------------------------------------------------------------------------
+    -- Memory Mapped Slave interface
+    ---------------------------------------------------------------------------
+    -- TSE MAC
+    -- . MOSI
+    mms_tse_address         : IN  STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+    mms_tse_write           : IN  STD_LOGIC;
+    mms_tse_read            : IN  STD_LOGIC;
+    mms_tse_writedata       : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    -- . MISO
+    mms_tse_readdata        : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    mms_tse_waitrequest     : OUT STD_LOGIC;
+    
+    -- ETH registers
+    -- . MOSI
+    mms_reg_address         : IN  STD_LOGIC_VECTOR(c_eth_reg_addr_w-1 DOWNTO 0);
+    mms_reg_write           : IN  STD_LOGIC;
+    mms_reg_read            : IN  STD_LOGIC;
+    mms_reg_writedata       : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    -- . MISO
+    mms_reg_readdata        : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    
+    -- ETH packet RAM
+    -- . MOSI
+    mms_ram_address         : IN  STD_LOGIC_VECTOR(c_eth_ram_addr_w-1 DOWNTO 0);
+    mms_ram_write           : IN  STD_LOGIC;
+    mms_ram_read            : IN  STD_LOGIC;
+    mms_ram_writedata       : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    -- . MISO
+    mms_ram_readdata        : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    
+    ---------------------------------------------------------------------------
+    -- Avalon Interrupt Sender interface: ins_*
+    ---------------------------------------------------------------------------
+    ins_interrupt_irq       : OUT STD_LOGIC;
+    
+    ---------------------------------------------------------------------------
+    -- Avalon Conduit interfaces: coe_*_export
+    ---------------------------------------------------------------------------
+    -- PHY interface
+    coe_eth_clk_export      : IN STD_LOGIC;
+    coe_eth_txp_export      : OUT STD_LOGIC;
+    coe_eth_rxp_export      : IN  STD_LOGIC;
+    
+    -- LED
+    coe_led_an_export       : OUT STD_LOGIC;
+    coe_led_link_export     : OUT STD_LOGIC;
+    coe_led_disp_err_export : OUT STD_LOGIC;
+    coe_led_char_err_export : OUT STD_LOGIC;
+    coe_led_crs_export      : OUT STD_LOGIC;
+    coe_led_col_export      : OUT STD_LOGIC
+  );
+END avs_eth;
+
+
+ARCHITECTURE wrap OF avs_eth IS
+
+  -- Wrap all records to STD_LOGIC
+  
+  -- ST UDP interface
+  SIGNAL udp_tx_snk_in_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+  SIGNAL udp_rx_src_in_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+  
+  -- MM interface
+  SIGNAL tse_sla_in        : t_mem_mosi;  -- ETH TSE MAC registers
+  SIGNAL tse_sla_out       : t_mem_miso;
+  SIGNAL reg_sla_in        : t_mem_mosi;  -- ETH control and status registers
+  SIGNAL reg_sla_out       : t_mem_miso;
+  SIGNAL ram_sla_in        : t_mem_mosi;  -- ETH rx frame and tx frame memory
+  SIGNAL ram_sla_out       : t_mem_miso;
+  
+  -- LED interface
+  SIGNAL tse_led           : t_tse_led;
+    
+BEGIN
+
+  -- Run internal ST at MM clock
+  -- Disable UDP off-load interface
+  udp_tx_snk_in_arr <= (OTHERS=>c_dp_sosi_rst);  -- default not valid if not used
+  udp_rx_src_in_arr <= (OTHERS=>c_dp_siso_rdy);  -- default ready if not used
+
+  -- TSE MAC
+  -- . MOSI
+  tse_sla_in.address  <= RESIZE_MEM_ADDRESS(mms_tse_address);
+  tse_sla_in.wr       <= mms_tse_write;
+  tse_sla_in.rd       <= mms_tse_read;
+  tse_sla_in.wrdata   <= RESIZE_MEM_DATA(mms_tse_writedata);
+  -- . MISO
+  mms_tse_readdata    <= tse_sla_out.rddata(c_word_w-1 DOWNTO 0);
+  mms_tse_waitrequest <= tse_sla_out.waitrequest;
+  
+  -- ETH registers
+  -- . MOSI
+  reg_sla_in.address  <= RESIZE_MEM_ADDRESS(mms_reg_address);
+  reg_sla_in.wr       <= mms_reg_write;
+  reg_sla_in.rd       <= mms_reg_read;
+  reg_sla_in.wrdata   <= RESIZE_MEM_DATA(mms_reg_writedata);
+  -- . MISO
+  mms_reg_readdata    <= reg_sla_out.rddata(c_word_w-1 DOWNTO 0);
+  
+  -- ETH packet RAM
+  -- . MOSI
+  ram_sla_in.address  <= RESIZE_MEM_ADDRESS(mms_ram_address);
+  ram_sla_in.wr       <= mms_ram_write;
+  ram_sla_in.rd       <= mms_ram_read;
+  ram_sla_in.wrdata   <= RESIZE_MEM_DATA(mms_ram_writedata);
+  -- . MISO
+  mms_ram_readdata    <= ram_sla_out.rddata(c_word_w-1 DOWNTO 0);
+  
+  -- LEDs
+  coe_led_an_export       <= tse_led.an;
+  coe_led_link_export     <= tse_led.link;
+  coe_led_disp_err_export <= tse_led.disp_err;
+  coe_led_char_err_export <= tse_led.char_err;
+  coe_led_crs_export      <= tse_led.crs;
+  coe_led_col_export      <= tse_led.col;
+  
+  u_eth : ENTITY work.eth
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst            => csi_mm_reset,        -- reset synchronous with mm_clk
+    mm_clk            => csi_mm_clk,          -- memory-mapped bus clock
+    eth_clk           => coe_eth_clk_export,  -- ethernet phy reference clock
+    st_rst            => csi_mm_reset,        -- reset synchronous with st_clk
+    st_clk            => csi_mm_clk,          -- packet stream clock
+    
+    -- UDP transmit interface
+    udp_tx_snk_in_arr  => udp_tx_snk_in_arr,
+    udp_tx_snk_out_arr => OPEN,
+    -- UDP receive interface
+    udp_rx_src_in_arr  => udp_rx_src_in_arr,
+    udp_rx_src_out_arr => OPEN,
+
+    -- Memory Mapped Slaves
+    tse_sla_in        => tse_sla_in,         -- ETH TSE MAC registers
+    tse_sla_out       => tse_sla_out,
+    reg_sla_in        => reg_sla_in,         -- ETH control and status registers
+    reg_sla_out       => reg_sla_out,
+    reg_sla_interrupt => ins_interrupt_irq,  -- ETH interrupt
+    ram_sla_in        => ram_sla_in,         -- ETH rx frame and tx frame memory
+    ram_sla_out       => ram_sla_out,
+
+    -- PHY interface
+    eth_txp           => coe_eth_txp_export,
+    eth_rxp           => coe_eth_rxp_export,
+
+    -- LED interface
+    tse_led           => tse_led
+  );
+  
+END wrap;

libraries/io/eth/src/vhdl/avs_eth_coe.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: AVS wrapper to make a MM slave ports for ETH available as conduit
+-- Description:
+-- Remark:
+-- . The avs_eth_coe_hw.tcl determines the read latency per port
+
+LIBRARY IEEE, common_lib, tech_tse_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE work.eth_pkg.ALL;
+
+
+ENTITY avs_eth_coe IS
+  PORT (
+    ----------------------------------------------------------------------------
+    -- MM side
+    
+    -- Clock interface
+    csi_mm_reset               : IN  STD_LOGIC;
+    csi_mm_clk                 : IN  STD_LOGIC;
+    
+    -- TSE MAC
+    mms_tse_address            : IN  STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+    mms_tse_write              : IN  STD_LOGIC;
+    mms_tse_read               : IN  STD_LOGIC;
+    mms_tse_writedata          : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    mms_tse_readdata           : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- read latency is 0
+    mms_tse_waitrequest        : OUT STD_LOGIC;                              -- necessary because read latency is 0
+    
+    -- ETH registers
+    mms_reg_address            : IN  STD_LOGIC_VECTOR(c_eth_reg_addr_w-1 DOWNTO 0);
+    mms_reg_write              : IN  STD_LOGIC;
+    mms_reg_read               : IN  STD_LOGIC;
+    mms_reg_writedata          : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    mms_reg_readdata           : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- read latency is 1
+    
+    -- ETH packet RAM
+    mms_ram_address            : IN  STD_LOGIC_VECTOR(c_eth_ram_addr_w-1 DOWNTO 0);
+    mms_ram_write              : IN  STD_LOGIC;
+    mms_ram_read               : IN  STD_LOGIC;
+    mms_ram_writedata          : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    mms_ram_readdata           : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- read latency is 2
+    
+    -- Interrupt Sender interface
+    ins_interrupt_irq          : OUT STD_LOGIC;  -- relates to the ETH registers port
+    
+    ----------------------------------------------------------------------------
+    -- User side
+    
+    -- Clock interface
+    coe_reset_export           : OUT STD_LOGIC;
+    coe_clk_export             : OUT STD_LOGIC;
+    
+    -- TSE MAC
+    coe_tse_address_export     : OUT STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+    coe_tse_write_export       : OUT STD_LOGIC;
+    coe_tse_read_export        : OUT STD_LOGIC;
+    coe_tse_writedata_export   : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    coe_tse_readdata_export    : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    coe_tse_waitrequest_export : IN  STD_LOGIC;
+    
+    -- ETH registers
+    coe_reg_address_export     : OUT STD_LOGIC_VECTOR(c_eth_reg_addr_w-1 DOWNTO 0);
+    coe_reg_write_export       : OUT STD_LOGIC;
+    coe_reg_read_export        : OUT STD_LOGIC;
+    coe_reg_writedata_export   : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    coe_reg_readdata_export    : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    
+    -- ETH packet RAM
+    coe_ram_address_export     : OUT STD_LOGIC_VECTOR(c_eth_ram_addr_w-1 DOWNTO 0);
+    coe_ram_write_export       : OUT STD_LOGIC;
+    coe_ram_read_export        : OUT STD_LOGIC;
+    coe_ram_writedata_export   : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    coe_ram_readdata_export    : IN  STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+    
+    -- Interrupt Sender interface
+    coe_irq_export             : IN  STD_LOGIC
+  );
+END avs_eth_coe;
+
+
+ARCHITECTURE wrap OF avs_eth_coe IS
+BEGIN
+
+  ------------------------------------------------------------------------------
+  -- Wires
+  
+  -- Clock interface
+  coe_reset_export         <= csi_mm_reset;
+  coe_clk_export           <= csi_mm_clk;
+  
+  -- TSE MAC
+  coe_tse_address_export   <= mms_tse_address;
+  coe_tse_write_export     <= mms_tse_write;
+  coe_tse_read_export      <= mms_tse_read;
+  coe_tse_writedata_export <= mms_tse_writedata;      
+  mms_tse_readdata         <= coe_tse_readdata_export;
+  mms_tse_waitrequest      <= coe_tse_waitrequest_export;
+                                                            
+  -- ETH registers
+  coe_reg_address_export   <= mms_reg_address;
+  coe_reg_write_export     <= mms_reg_write;
+  coe_reg_read_export      <= mms_reg_read;
+  coe_reg_writedata_export <= mms_reg_writedata;
+  mms_reg_readdata         <= coe_reg_readdata_export;
+                                                            
+  -- ETH packet RAM
+  coe_ram_address_export   <= mms_ram_address;
+  coe_ram_write_export     <= mms_ram_write;
+  coe_ram_read_export      <= mms_ram_read;
+  coe_ram_writedata_export <= mms_ram_writedata;
+  mms_ram_readdata         <= coe_ram_readdata_export;
+                                                            
+  -- Interrupt Sender interface
+  ins_interrupt_irq        <= coe_irq_export;
+
+END wrap;

libraries/io/eth/tb/vhdl/tb_tb_eth.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, tech_tse_lib;
+USE IEEE.std_logic_1164.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+
+
+ENTITY tb_tb_eth IS
+END tb_tb_eth;
+
+
+ARCHITECTURE tb OF tb_tb_eth IS
+
+BEGIN
+
+  -- Try ETH settings : GENERIC MAP (g_data_type => )
+  
+  u_use_symbols : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_symbols);
+  u_use_counter : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_counter);
+  u_use_arp     : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_arp    );
+  u_use_ping    : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_ping   );
+  u_use_udp     : ENTITY work.tb_eth GENERIC MAP (c_tb_tse_data_type_udp    );
+  
+END tb;