Added ip_arria10 component for 24x 10gbase_r and 24 transceiver reset controller.

libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd

@@ -72,6 +72,50 @@ PACKAGE tech_10gbase_r_component_pkg IS
     rx_enh_blk_lock         : out std_logic_vector(0 downto 0)                      --         rx_enh_blk_lock.rx_enh_blk_lock
   );
   END COMPONENT;
+  
+  COMPONENT ip_arria10_phy_10gbase_r_24 IS
+  PORT (
+    rx_analogreset          : in  std_logic_vector(23 downto 0)   := (others => '0'); --          rx_analogreset.rx_analogreset
+    rx_cal_busy             : out std_logic_vector(23 downto 0);                      --             rx_cal_busy.rx_cal_busy
+    rx_cdr_refclk0          : in  std_logic                       := '0';             --          rx_cdr_refclk0.clk
+    rx_clkout               : out std_logic_vector(23 downto 0);                      --               rx_clkout.clk
+    rx_control              : out std_logic_vector(191 downto 0);                     --              rx_control.rx_control
+    rx_coreclkin            : in  std_logic_vector(23 downto 0)   := (others => '0'); --            rx_coreclkin.clk
+    rx_digitalreset         : in  std_logic_vector(23 downto 0)   := (others => '0'); --         rx_digitalreset.rx_digitalreset
+    rx_enh_blk_lock         : out std_logic_vector(23 downto 0);                      --         rx_enh_blk_lock.rx_enh_blk_lock
+    rx_enh_data_valid       : out std_logic_vector(23 downto 0);                      --       rx_enh_data_valid.rx_enh_data_valid
+    rx_enh_fifo_del         : out std_logic_vector(23 downto 0);                      --         rx_enh_fifo_del.rx_enh_fifo_del
+    rx_enh_fifo_empty       : out std_logic_vector(23 downto 0);                      --       rx_enh_fifo_empty.rx_enh_fifo_empty
+    rx_enh_fifo_full        : out std_logic_vector(23 downto 0);                      --        rx_enh_fifo_full.rx_enh_fifo_full
+    rx_enh_fifo_insert      : out std_logic_vector(23 downto 0);                      --      rx_enh_fifo_insert.rx_enh_fifo_insert
+    rx_enh_highber          : out std_logic_vector(23 downto 0);                      --          rx_enh_highber.rx_enh_highber
+    rx_is_lockedtodata      : out std_logic_vector(23 downto 0);                      --      rx_is_lockedtodata.rx_is_lockedtodata
+    rx_is_lockedtoref       : out std_logic_vector(23 downto 0);                      --       rx_is_lockedtoref.rx_is_lockedtoref
+    rx_parallel_data        : out std_logic_vector(1535 downto 0);                    --        rx_parallel_data.rx_parallel_data
+    rx_serial_data          : in  std_logic_vector(23 downto 0)   := (others => '0'); --          rx_serial_data.rx_serial_data
+    tx_analogreset          : in  std_logic_vector(23 downto 0)   := (others => '0'); --          tx_analogreset.tx_analogreset
+    tx_cal_busy             : out std_logic_vector(23 downto 0);                      --             tx_cal_busy.tx_cal_busy
+    tx_clkout               : out std_logic_vector(23 downto 0);                      --               tx_clkout.clk
+    tx_control              : in  std_logic_vector(191 downto 0)  := (others => '0'); --              tx_control.tx_control
+    tx_coreclkin            : in  std_logic_vector(23 downto 0)   := (others => '0'); --            tx_coreclkin.clk
+    tx_digitalreset         : in  std_logic_vector(23 downto 0)   := (others => '0'); --         tx_digitalreset.tx_digitalreset
+    tx_enh_data_valid       : in  std_logic_vector(23 downto 0)   := (others => '0'); --       tx_enh_data_valid.tx_enh_data_valid
+    tx_enh_fifo_empty       : out std_logic_vector(23 downto 0);                      --       tx_enh_fifo_empty.tx_enh_fifo_empty
+    tx_enh_fifo_full        : out std_logic_vector(23 downto 0);                      --        tx_enh_fifo_full.tx_enh_fifo_full
+    tx_enh_fifo_pempty      : out std_logic_vector(23 downto 0);                      --      tx_enh_fifo_pempty.tx_enh_fifo_pempty
+    tx_enh_fifo_pfull       : out std_logic_vector(23 downto 0);                      --       tx_enh_fifo_pfull.tx_enh_fifo_pfull
+    tx_err_ins              : in  std_logic_vector(23 downto 0)   := (others => '0'); --              tx_err_ins.tx_err_ins
+    tx_parallel_data        : in  std_logic_vector(1535 downto 0) := (others => '0'); --        tx_parallel_data.tx_parallel_data
+    tx_pma_div_clkout       : out std_logic_vector(23 downto 0);                      --       tx_pma_div_clkout.clk
+    tx_serial_clk0          : in  std_logic_vector(23 downto 0)   := (others => '0'); --          tx_serial_clk0.clk
+    tx_serial_data          : out std_logic_vector(23 downto 0);                      --          tx_serial_data.tx_serial_data
+    unused_rx_control       : out std_logic_vector(287 downto 0);                     --       unused_rx_control.unused_rx_control
+    unused_rx_parallel_data : out std_logic_vector(1535 downto 0);                    -- unused_rx_parallel_data.unused_rx_parallel_data
+    unused_tx_control       : in  std_logic_vector(215 downto 0)  := (others => '0'); --       unused_tx_control.unused_tx_control
+    unused_tx_parallel_data : in  std_logic_vector(1535 downto 0) := (others => '0')  -- unused_tx_parallel_data.unused_tx_parallel_data
+  );  
+  END COMPONENT;
+
 
   COMPONENT ip_arria10_transceiver_pll_10g IS
   PORT (
@@ -101,5 +145,24 @@ PACKAGE tech_10gbase_r_component_pkg IS
     rx_cal_busy        : in  std_logic_vector(0 downto 0) := (others => '0')  --        rx_cal_busy.rx_cal_busy
   );
   END COMPONENT;
-  
+
+  COMPONENT ip_arria10_transceiver_reset_controller_24 IS
+  PORT (
+    clock              : in  std_logic                     := '0';             --              clock.clk
+    pll_locked         : in  std_logic_vector(0 downto 0)  := (others => '0'); --         pll_locked.pll_locked
+    pll_powerdown      : out std_logic_vector(0 downto 0);                     --      pll_powerdown.pll_powerdown
+    pll_select         : in  std_logic_vector(0 downto 0)  := (others => '0'); --         pll_select.pll_select
+    reset              : in  std_logic                     := '0';             --              reset.reset
+    rx_analogreset     : out std_logic_vector(23 downto 0);                    --     rx_analogreset.rx_analogreset
+    rx_cal_busy        : in  std_logic_vector(23 downto 0) := (others => '0'); --        rx_cal_busy.rx_cal_busy
+    rx_digitalreset    : out std_logic_vector(23 downto 0);                    --    rx_digitalreset.rx_digitalreset
+    rx_is_lockedtodata : in  std_logic_vector(23 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+    rx_ready           : out std_logic_vector(23 downto 0);                    --           rx_ready.rx_ready
+    tx_analogreset     : out std_logic_vector(23 downto 0);                    --     tx_analogreset.tx_analogreset
+    tx_cal_busy        : in  std_logic_vector(23 downto 0) := (others => '0'); --        tx_cal_busy.tx_cal_busy
+    tx_digitalreset    : out std_logic_vector(23 downto 0);                    --    tx_digitalreset.tx_digitalreset
+    tx_ready           : out std_logic_vector(23 downto 0)                     --           tx_ready.tx_ready
+  );
+  END COMPONENT;
+
 END tech_10gbase_r_component_pkg;