Ported common RAM, ROM components from...

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.

libraries/technology/altera/altera_mf/altera_mf_ram_cr_cw.vhd

+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altera_mf_ram_cr_cw.vhd
+-- Megafunction Name(s):
+--      altsyncram
+--
+-- Simulation Library Files(s):
+--      altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2011 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+ENTITY altera_mf_ram_cr_cw IS
+  GENERIC (
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    rdclock   : IN  STD_LOGIC ;
+    rdclocken : IN  STD_LOGIC  := '1';
+    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    wrclock   : IN  STD_LOGIC  := '1';
+    wrclocken : IN  STD_LOGIC  := '1';
+    wren      : IN  STD_LOGIC  := '0';
+    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+END altera_mf_ram_cr_cw;
+
+
+ARCHITECTURE SYN OF altera_mf_ram_cr_cw IS
+
+  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+  
+  SIGNAL sub_wire0  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+
+
+  COMPONENT altsyncram
+  GENERIC (
+    address_aclr_b    : STRING;
+    address_reg_b   : STRING;
+    clock_enable_input_a    : STRING;
+    clock_enable_input_b    : STRING;
+    clock_enable_output_b   : STRING;
+    intended_device_family    : STRING;
+    lpm_type    : STRING;
+    numwords_a    : NATURAL;
+    numwords_b    : NATURAL;
+    operation_mode    : STRING;
+    outdata_aclr_b    : STRING;
+    outdata_reg_b   : STRING;
+    power_up_uninitialized    : STRING;
+    widthad_a   : NATURAL;
+    widthad_b   : NATURAL;
+    width_a   : NATURAL;
+    width_b   : NATURAL;
+    width_byteena_a   : NATURAL
+  );
+  PORT (
+      clock0    : IN  STD_LOGIC ;
+      clocken1  : IN  STD_LOGIC ;
+      wren_a    : IN  STD_LOGIC ;
+      address_b : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+      clock1    : IN  STD_LOGIC ;
+      clocken0  : IN  STD_LOGIC ;
+      address_a : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+      data_a    : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+      q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+BEGIN
+  q    <= sub_wire0(g_dat_w-1 DOWNTO 0);
+
+  altsyncram_component : altsyncram
+  GENERIC MAP (
+    address_aclr_b => "NONE",
+    address_reg_b => "CLOCK1",
+    clock_enable_input_a => "NORMAL",
+    clock_enable_input_b => "NORMAL",
+    clock_enable_output_b => "NORMAL",
+    intended_device_family => "Stratix IV",
+    lpm_type => "altsyncram",
+    numwords_a => g_nof_words,
+    numwords_b => g_nof_words,
+    operation_mode => "DUAL_PORT",
+    outdata_aclr_b => "NONE",
+    outdata_reg_b => c_outdata_reg_b,
+    power_up_uninitialized => "FALSE",
+    widthad_a => g_adr_w,
+    widthad_b => g_adr_w,
+    width_a => g_dat_w,
+    width_b => g_dat_w,
+    width_byteena_a => 1
+  )
+  PORT MAP (
+    clock0 => wrclock,
+    clocken1 => rdclocken,
+    wren_a => wren,
+    address_b => rdaddress,
+    clock1 => rdclock,
+    clocken0 => wrclocken,
+    address_a => wraddress,
+    data_a => data,
+    q_b => sub_wire0
+  );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "fft_3n1024sin.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL "rdaddress[4..0]"
+-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
+-- Retrieval info: USED_PORT: rdclocken 0 0 0 0 INPUT VCC "rdclocken"
+-- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL "wraddress[4..0]"
+-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
+-- Retrieval info: USED_PORT: wrclocken 0 0 0 0 INPUT VCC "wrclocken"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
+-- Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 wrclocken 0 0 0 0
+-- Retrieval info: CONNECT: @clocken1 0 0 0 0 rdclocken 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_cr_cw_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf

libraries/technology/altera/altera_mf/altera_mf_ram_crw_crw.vhd

+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altera_mf_ram_crw_crw.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.0 Build 218 06/27/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+ENTITY altera_mf_ram_crw_crw IS
+  GENERIC (
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		enable_a		: IN STD_LOGIC  := '1';
+		enable_b		: IN STD_LOGIC  := '1';
+		rden_a		: IN STD_LOGIC  := '1';
+		rden_b		: IN STD_LOGIC  := '1';
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+	);
+END altera_mf_ram_crw_crw;
+
+
+ARCHITECTURE SYN OF altera_mf_ram_crw_crw IS
+
+  FUNCTION sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
+  BEGIN
+    IF sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
+  END;
+  
+  CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clocken0	: IN STD_LOGIC ;
+			clocken1	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			rden_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			rden_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(g_dat_w-1 DOWNTO 0);
+	q_b    <= sub_wire1(g_dat_w-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		init_file => g_init_file,
+		intended_device_family => "Stratix IV",
+		lpm_type => "altsyncram",
+		numwords_a => g_nof_words,
+		numwords_b => g_nof_words,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => c_outdata_reg_a,
+		outdata_reg_b => c_outdata_reg_b,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => g_adr_w,
+		widthad_b => g_adr_w,
+		width_a => g_dat_w,
+		width_b => g_dat_w,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		clocken0 => enable_a,
+		clocken1 => enable_b,
+		wren_a => wren_a,
+		rden_a => rden_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		rden_b => rden_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "576"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "fft_3n1024sin.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "fft_3n1024sin.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+-- Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
+-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC "enable_a"
+-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC "enable_b"
+-- Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
+-- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
+-- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
+-- Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
+-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
+-- Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
+-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
+-- Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crw_crw_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

libraries/technology/altera/altera_mf/altera_mf_ram_crwk_crw.vhd

+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altera_mf_ram_crwk_crw.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.0 Build 218 06/27/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+ENTITY altera_mf_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
+  GENERIC (
+    g_adr_a_w     : NATURAL := 5;
+    g_dat_a_w     : NATURAL := 32;
+    g_adr_b_w     : NATURAL := 7;
+    g_dat_b_w     : NATURAL := 8;
+    g_nof_words_a : NATURAL := 2**5;
+    g_nof_words_b : NATURAL := 2**7;
+    g_rd_latency  : NATURAL := 2;     -- choose 1 or 2
+    g_init_file   : STRING  := "UNUSED"
+  );
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+		enable_a		: IN STD_LOGIC  := '1';
+		enable_b		: IN STD_LOGIC  := '1';
+		rden_a		: IN STD_LOGIC  := '1';
+		rden_b		: IN STD_LOGIC  := '1';
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+	);
+END altera_mf_ram_crwk_crw;
+
+
+ARCHITECTURE SYN OF altera_mf_ram_crwk_crw IS
+
+  FUNCTION sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
+  BEGIN
+    IF sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
+  END;
+  
+  CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		init_file_layout		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			clocken1	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+			rden_a	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+			rden_b	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+			clocken0	: IN STD_LOGIC ;
+			data_b	: IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(g_dat_a_w-1 DOWNTO 0);
+	q_b    <= sub_wire1(g_dat_b_w-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_a => "NORMAL",
+		clock_enable_output_b => "NORMAL",
+		indata_reg_b => "CLOCK1",
+		init_file => g_init_file,
+		init_file_layout => "PORT_B",
+		intended_device_family => "Stratix IV",
+		lpm_type => "altsyncram",
+		numwords_a => g_nof_words_a,
+		numwords_b => g_nof_words_b,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => c_outdata_reg_a,
+		outdata_reg_b => c_outdata_reg_b,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => g_adr_a_w,
+		widthad_b => g_adr_b_w,
+		width_a => g_dat_a_w,
+		width_b => g_dat_b_w,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		clock0 => clock_a,
+		clocken1 => enable_b,
+		wren_a => wren_a,
+		clock1 => clock_b,
+		rden_a => rden_a,
+		wren_b => wren_b,
+		address_a => address_a,
+		data_a => data_a,
+		rden_b => rden_b,
+		address_b => address_b,
+		clocken0 => enable_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "../../Lofar/pfs/src/data/pfs_coefsbuf_1024.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "../../Lofar/pfs/src/data/pfs_coefsbuf_1024.hex"
+-- Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
+-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC "enable_a"
+-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC "enable_b"
+-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
+-- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
+-- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0
+-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
+-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_crwk_crw_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

libraries/technology/altera/altera_mf/altera_mf_ram_r_w.vhd

+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altera_mf_ram_r_w.vhd
+-- Megafunction Name(s):
+--      altsyncram
+--
+-- Simulation Library Files(s):
+--      altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altera_mf_ram_r_w IS
+  GENERIC (
+    g_adr_w     : NATURAL := 5;
+    g_dat_w     : NATURAL := 8;
+    g_nof_words : NATURAL := 2**5;
+    g_init_file : STRING  := "UNUSED"
+  );
+  PORT (
+    clock       : IN STD_LOGIC  := '1';
+    enable      : IN STD_LOGIC  := '1';
+    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    wren        : IN STD_LOGIC  := '0';
+    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+  );
+END altera_mf_ram_r_w;
+
+
+ARCHITECTURE SYN OF altera_mf_ram_r_w IS
+
+  SIGNAL sub_wire0  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+  COMPONENT altsyncram
+  GENERIC (
+    address_aclr_b    : STRING;
+    address_reg_b   : STRING;
+    clock_enable_input_a    : STRING;
+    clock_enable_input_b    : STRING;
+    clock_enable_output_b   : STRING;
+    init_file   : STRING;
+    intended_device_family    : STRING;
+    lpm_type    : STRING;
+    numwords_a    : NATURAL;
+    numwords_b    : NATURAL;
+    operation_mode    : STRING;
+    outdata_aclr_b    : STRING;
+    outdata_reg_b   : STRING;
+    power_up_uninitialized    : STRING;
+    read_during_write_mode_mixed_ports    : STRING;
+    widthad_a   : NATURAL;
+    widthad_b   : NATURAL;
+    width_a   : NATURAL;
+    width_b   : NATURAL;
+    width_byteena_a   : NATURAL
+  );
+  PORT (
+      clocken0  : IN STD_LOGIC ;
+      wren_a  : IN STD_LOGIC ;
+      clock0  : IN STD_LOGIC ;
+      address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+      address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+      q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+      data_a  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+BEGIN
+  q    <= sub_wire0(g_dat_w-1 DOWNTO 0);
+
+  altsyncram_component : altsyncram
+  GENERIC MAP (
+    address_aclr_b => "NONE",
+    address_reg_b => "CLOCK0",
+    clock_enable_input_a => "NORMAL",
+    clock_enable_input_b => "NORMAL",
+    clock_enable_output_b => "NORMAL",
+    init_file => g_init_file,
+    intended_device_family => "Stratix IV",
+    lpm_type => "altsyncram",
+    numwords_a => g_nof_words,
+    numwords_b => g_nof_words,
+    operation_mode => "DUAL_PORT",
+    outdata_aclr_b => "NONE",
+    outdata_reg_b => "CLOCK0",
+    power_up_uninitialized => "FALSE",
+    read_during_write_mode_mixed_ports => "DONT_CARE",
+    widthad_a => g_adr_w,
+    widthad_b => g_adr_w,
+    width_a => g_dat_w,
+    width_b => g_dat_w,
+    width_byteena_a => 1
+  )
+  PORT MAP (
+    clocken0 => enable,
+    wren_a => wren,
+    clock0 => clock,
+    address_a => wraddress,
+    address_b => rdaddress,
+    data_a => data,
+    q_b => sub_wire0
+  );
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "fft_3n1024sin.hex"
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "fft_3n1024sin.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC enable
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL rdaddress[4..0]
+-- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
+-- Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_ram_r_w_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

libraries/technology/altera/altera_mf/altera_mf_rom_r.vhd

+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altera_mf_rom_r.vhd
+-- Megafunction Name(s):
+--      altsyncram
+--
+-- Simulation Library Files(s):
+--      altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altera_mf_rom_r IS
+  GENERIC (
+    g_adr_w     : NATURAL := 5;
+    g_dat_w     : NATURAL := 8;
+    g_nof_words : NATURAL := 2**5;
+    g_init_file : STRING  := "UNUSED"
+  );
+  PORT (
+    address   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    clock     : IN STD_LOGIC  := '1';
+    clken     : IN STD_LOGIC  := '1';
+    q         : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+  );
+END altera_mf_rom_r;
+
+
+ARCHITECTURE SYN OF altera_mf_rom_r IS
+
+  SIGNAL sub_wire0  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+  COMPONENT altsyncram
+  GENERIC (
+    address_aclr_a    : STRING;
+    clock_enable_input_a    : STRING;
+    clock_enable_output_a   : STRING;
+    init_file   : STRING;
+    intended_device_family    : STRING;
+    lpm_hint    : STRING;
+    lpm_type    : STRING;
+    numwords_a    : NATURAL;
+    operation_mode    : STRING;
+    outdata_aclr_a    : STRING;
+    outdata_reg_a   : STRING;
+    widthad_a   : NATURAL;
+    width_a   : NATURAL;
+    width_byteena_a   : NATURAL
+  );
+  PORT (
+      clocken0  : IN STD_LOGIC ;
+      clock0  : IN STD_LOGIC ;
+      address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+      q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+BEGIN
+  q    <= sub_wire0(g_dat_w-1 DOWNTO 0);
+
+  altsyncram_component : altsyncram
+  GENERIC MAP (
+    address_aclr_a => "NONE",
+    clock_enable_input_a => "NORMAL",
+    clock_enable_output_a => "NORMAL",
+    init_file => g_init_file,
+    intended_device_family => "Stratix IV",
+    lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+    lpm_type => "altsyncram",
+    numwords_a => g_nof_words,
+    operation_mode => "ROM",
+    outdata_aclr_a => "NONE",
+    outdata_reg_a => "CLOCK0",
+    widthad_a => g_adr_w,
+    width_a => g_dat_w,
+    width_byteena_a => 1
+  )
+  PORT MAP (
+    clocken0 => clken,
+    clock0 => clock,
+    address_a => address,
+    q_a => sub_wire0
+  );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: Clken NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "fft_2n1024cos.hex"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "18"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "fft_2n1024cos.hex"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0]
+-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
+-- Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
+-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
+-- Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_rom_r_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

libraries/technology/altera/altera_mf/hdllib.cfg

+hdl_lib_name = ip_altera_mf
+hdl_library_clause_name = ip_altera_mf_lib
+hdl_lib_uses = technology
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    altera_mf_ram_cr_cw.vhd
+    altera_mf_ram_crw_crw.vhd
+    altera_mf_ram_crwk_crw.vhd
+    altera_mf_ram_r_w.vhd
+    altera_mf_rom_r.vhd
+    
+test_bench_files =

libraries/technology/base/hdllib.cfg

+hdl_lib_name = technology
+hdl_library_clause_name = technology_lib
+hdl_lib_uses =
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    technology_pkg.vhd
+    technology_select_pkg.vhd
+    
+test_bench_files =

libraries/technology/base/technology_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE technology_pkg IS
+
+  -- Technology identifiers
+  CONSTANT c_tech_inferred           : INTEGER := 0;
+  CONSTANT c_tech_stratixiv          : INTEGER := 1;
+  CONSTANT c_tech_arria10            : INTEGER := 2;
+  CONSTANT c_tech_stratix10          : INTEGER := 3;
+  CONSTANT c_tech_nof_technologies   : INTEGER := 4;
+
+  -- Functions
+  FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING;
+  
+END technology_pkg;
+
+PACKAGE BODY technology_pkg IS
+
+  FUNCTION tech_sel_a_b(sel : BOOLEAN; a, b : STRING) RETURN STRING IS
+  BEGIN
+    IF sel=TRUE THEN RETURN a; ELSE RETURN b; END IF;
+  END;
+  
+END technology_pkg;
\ No newline at end of file

libraries/technology/base/technology_select_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Define default technology selection value for g_technology.
+-- Description:
+--   In case g_technology is not overruled by the application design then the
+--   g_technology defaults to c_tech_select_default.
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE work.technology_pkg.ALL;
+
+PACKAGE technology_select_pkg IS
+
+  CONSTANT c_tech_select_default : INTEGER := c_tech_stratixiv;
+  
+END technology_select_pkg;

libraries/technology/memory/hdllib.cfg

+hdl_lib_name = technology_memory
+hdl_library_clause_name = technology_memory_lib
+hdl_lib_uses = technology ip_altera_mf
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    memory_component_pkg.vhd
+    memory_ram_cr_cw.vhd
+    memory_ram_crw_crw.vhd
+    memory_ram_crwk_crw.vhd
+    memory_ram_r_w.vhd
+
+test_bench_files =

libraries/technology/memory/memory_component_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE memory_component_pkg IS
+
+  -----------------------------------------------------------------------------
+  -- altera_mf
+  -----------------------------------------------------------------------------
+  
+  COMPONENT altera_mf_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
+  GENERIC (
+    g_adr_a_w     : NATURAL := 5;
+    g_dat_a_w     : NATURAL := 32;
+    g_adr_b_w     : NATURAL := 7;
+    g_dat_b_w     : NATURAL := 8;
+    g_nof_words_a : NATURAL := 2**5;
+    g_nof_words_b : NATURAL := 2**7;
+    g_rd_latency  : NATURAL := 2;     -- choose 1 or 2
+    g_init_file   : STRING  := "UNUSED"
+  );
+  PORT (
+    address_a   : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+    address_b   : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+    clock_a   : IN STD_LOGIC  := '1';
+    clock_b   : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+    enable_a    : IN STD_LOGIC  := '1';
+    enable_b    : IN STD_LOGIC  := '1';
+    rden_a    : IN STD_LOGIC  := '1';
+    rden_b    : IN STD_LOGIC  := '1';
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a   : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+    q_b   : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT altera_mf_ram_crw_crw IS
+  GENERIC (
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT (
+    address_a   : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    address_b   : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    clock_a   : IN STD_LOGIC  := '1';
+    clock_b   : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    enable_a    : IN STD_LOGIC  := '1';
+    enable_b    : IN STD_LOGIC  := '1';
+    rden_a    : IN STD_LOGIC  := '1';
+    rden_b    : IN STD_LOGIC  := '1';
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a   : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    q_b   : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT altera_mf_ram_cr_cw IS
+  GENERIC (
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT (
+    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    rdclock   : IN  STD_LOGIC ;
+    rdclocken : IN  STD_LOGIC  := '1';
+    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    wrclock   : IN  STD_LOGIC  := '1';
+    wrclocken : IN  STD_LOGIC  := '1';
+    wren      : IN  STD_LOGIC  := '0';
+    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT altera_mf_ram_r_w IS
+  GENERIC (
+    g_adr_w     : NATURAL := 5;
+    g_dat_w     : NATURAL := 8;
+    g_nof_words : NATURAL := 2**5;
+    g_init_file : STRING  := "UNUSED"
+  );
+  PORT (
+    clock       : IN STD_LOGIC  := '1';
+    enable      : IN STD_LOGIC  := '1';
+    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    wren        : IN STD_LOGIC  := '0';
+    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT altera_mf_rom_r IS
+  GENERIC (
+    g_adr_w     : NATURAL := 5;
+    g_dat_w     : NATURAL := 8;
+    g_nof_words : NATURAL := 2**5;
+    g_init_file : STRING  := "UNUSED"
+  );
+  PORT (
+    address   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    clock     : IN STD_LOGIC  := '1';
+    clken     : IN STD_LOGIC  := '1';
+    q         : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+
+END memory_component_pkg;

libraries/technology/memory/memory_ram_cr_cw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.memory_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY memory_ram_cr_cw IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    rdclock   : IN  STD_LOGIC ;
+    rdclocken : IN  STD_LOGIC  := '1';
+    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    wrclock   : IN  STD_LOGIC  := '1';
+    wrclocken : IN  STD_LOGIC  := '1';
+    wren      : IN  STD_LOGIC  := '0';
+    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+END memory_ram_cr_cw;
+
+ARCHITECTURE str OF memory_ram_cr_cw IS
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_ram_cr_cw
+    GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (data, rdaddress, rdclock, rdclocken, wraddress, wrclock, wrclocken, wren, q);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/memory/memory_ram_crw_crw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.memory_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_altera_mf_lib;
+
+ENTITY memory_ram_crw_crw IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+    clock_a   : IN STD_LOGIC  := '1';
+    clock_b   : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    enable_a  : IN STD_LOGIC  := '1';
+    enable_b  : IN STD_LOGIC  := '1';
+    rden_a    : IN STD_LOGIC  := '1';
+    rden_b    : IN STD_LOGIC  := '1';
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+  );
+END memory_ram_crw_crw;
+
+
+ARCHITECTURE str OF memory_ram_crw_crw IS
+
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_ram_crw_crw
+    GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
+    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/memory/memory_ram_crwk_crw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.memory_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY memory_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
+  GENERIC (
+    g_technology  : NATURAL := c_tech_select_default;
+    g_adr_a_w     : NATURAL := 5;
+    g_dat_a_w     : NATURAL := 32;
+    g_adr_b_w     : NATURAL := 7;
+    g_dat_b_w     : NATURAL := 8;
+    g_nof_words_a : NATURAL := 2**5;
+    g_nof_words_b : NATURAL := 2**7;
+    g_rd_latency  : NATURAL := 2;     -- choose 1 or 2
+    g_init_file   : STRING  := "UNUSED"
+  );
+  PORT
+  (
+    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+    clock_a   : IN STD_LOGIC  := '1';
+    clock_b   : IN STD_LOGIC ;
+    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+    enable_a  : IN STD_LOGIC  := '1';
+    enable_b  : IN STD_LOGIC  := '1';
+    rden_a    : IN STD_LOGIC  := '1';
+    rden_b    : IN STD_LOGIC  := '1';
+    wren_a    : IN STD_LOGIC  := '0';
+    wren_b    : IN STD_LOGIC  := '0';
+    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+  );
+END memory_ram_crwk_crw;
+
+
+ARCHITECTURE str OF memory_ram_crwk_crw IS
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_ram_crwk_crw
+    GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
+    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/memory/memory_ram_r_w.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.memory_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY memory_ram_r_w IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT (
+    clock       : IN STD_LOGIC  := '1';
+    enable      : IN STD_LOGIC  := '1';
+    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    wren        : IN STD_LOGIC  := '0';
+    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+  );
+END memory_ram_r_w;
+
+
+ARCHITECTURE str OF memory_ram_r_w IS
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_ram_r_w
+    GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_init_file)
+    PORT MAP (clock, enable, data, rdaddress, wraddress, wren, q);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/memory/memory_rom_r.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.memory_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY memory_rom_r IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_adr_w      : NATURAL := 5;
+    g_dat_w      : NATURAL := 8;
+    g_nof_words  : NATURAL := 2**5;
+    g_init_file  : STRING  := "UNUSED"
+  );
+  PORT (
+    address   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
+    clock     : IN STD_LOGIC  := '1';
+    clken     : IN STD_LOGIC  := '1';
+    q         : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+  );
+END memory_rom_r;
+
+ARCHITECTURE str OF memory_rom_r IS
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_rom_r
+    GENERIC MAP (g_adr_w, g_dat_w, g_nof_words, g_init_file)
+    PORT MAP (address, clock, clken, q);
+  END GENERATE;
+   
+END ARCHITECTURE;
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