Use tech_pll_xgmii_mac_clocks instead of ip_arria10_transceiver_pll_156_312_top.

libraries/technology/10gbase_r/hdllib.cfg

 hdl_lib_name = tech_10gbase_r
 hdl_library_clause_name = tech_10gbase_r_lib
-hdl_lib_uses = technology ip_arria10_phy_10gbase_r ip_arria10_transceiver_pll_156_312 ip_arria10_transceiver_pll_10g ip_arria10_transceiver_reset_controller_1 common
+hdl_lib_uses = technology tech_pll ip_arria10_phy_10gbase_r ip_arria10_transceiver_pll_10g ip_arria10_transceiver_reset_controller_1 common
 hdl_lib_technology = 
 
 build_dir_sim = $HDL_BUILD_DIR

libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd

@@ -27,14 +27,14 @@
 --   > as 10
 --   > run 100 us
 
-LIBRARY IEEE, technology_lib, common_lib;
+LIBRARY IEEE, technology_lib, tech_pll_lib, common_lib;
 USE IEEE.std_logic_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
 USE technology_lib.technology_pkg.ALL;
 USE technology_lib.technology_select_pkg.ALL;
-USE work.tech_10gbase_r_component_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
 
 
 ENTITY tb_tech_10gbase_r IS
@@ -51,10 +51,9 @@ ARCHITECTURE tb OF tb_tech_10gbase_r IS
   CONSTANT c_sim               : BOOLEAN:= TRUE;
   CONSTANT phy_loopback_delay  : TIME :=  1 ns;
   
-  SIGNAL tr_ref_clk        : STD_LOGIC := '0';
-  SIGNAL clk_312           : STD_LOGIC;    -- 312.5 MHz
-  SIGNAL clk_156           : STD_LOGIC;    -- 156.25 MHz
-  SIGNAL rst_156           : STD_LOGIC;    -- reset for clk_156 clock domain
+  SIGNAL tr_ref_clk_644    : STD_LOGIC := '0';
+  SIGNAL clk_156           : STD_LOGIC;
+  SIGNAL rst_156           : STD_LOGIC;
 
   -- XGMII interface
   SIGNAL xgmii_tx_dc_arr   : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);
@@ -66,7 +65,19 @@ ARCHITECTURE tb OF tb_tech_10gbase_r IS
   
 BEGIN
 
-  tr_ref_clk <= NOT tr_ref_clk AFTER tech_10gbase_r_ref_clk_period/2;
+  tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER tech_pll_clk_644_period/2;
+
+  pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+  GENERIC MAP (
+    g_technology => g_technology
+  )
+  PORT MAP (
+    refclk_644 => tr_ref_clk_644,
+    clk_156    => clk_156,
+    clk_312    => OPEN,
+    rst_156    => rst_156,
+    rst_312    => OPEN
+  );
 
   dut : ENTITY work.tech_10gbase_r
   GENERIC MAP (
@@ -75,11 +86,10 @@ BEGIN
     g_nof_channels     => g_nof_channels
   )
   PORT MAP (
-    -- Transceiver PLL reference clock
-    tr_ref_clk              => tr_ref_clk,   -- 644.531250 MHz
+    -- Transceiver ATX PLL reference clock
+    tr_ref_clk_644     => tr_ref_clk_644,
     
-    -- Derived clocks
-    clk_312            => clk_312,
+    -- XGMII clocks
     clk_156            => clk_156,
     rst_156            => rst_156,
 

libraries/technology/10gbase_r/tech_10gbase_r.vhd

@@ -34,13 +34,12 @@ ENTITY tech_10gbase_r IS
     g_nof_channels   : NATURAL := 1
   );
   PORT (
-    -- Transceiver PLL reference clock
-    tr_ref_clk              : IN  STD_LOGIC;    -- 644.531250 MHz
+    -- Transceiver ATX PLL reference clock
+    tr_ref_clk_644          : IN  STD_LOGIC;   -- 644.531250 MHz
     
-    -- Derived clocks
-    clk_312                 : OUT STD_LOGIC;    -- 312.5 MHz
-    clk_156                 : OUT STD_LOGIC;    -- 156.25 MHz
-    rst_156                 : OUT STD_LOGIC;    -- reset for clk_156_in clock domain
+    -- XGMII clocks
+    clk_156                 : IN STD_LOGIC;    -- 156.25 MHz
+    rst_156                 : IN STD_LOGIC;
 
     -- XGMII interface
     xgmii_tx_dc_arr         : IN  t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
@@ -55,17 +54,13 @@ END tech_10gbase_r;
 
 ARCHITECTURE str OF tech_10gbase_r IS  
   
-  SIGNAL clk_156_out        : STD_LOGIC;    -- connect to clk_156_out to clk_156_in to avoid delta-cycle differences in simulation
-  
 BEGIN
  
-  clk_156 <= clk_156_out;
-  
   gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
     u0 : ENTITY work.tech_10gbase_r_arria10
     GENERIC MAP (g_sim, g_nof_channels)
-    PORT MAP (tr_ref_clk,
-              clk_312, clk_156_out, clk_156_out, rst_156,
+    PORT MAP (tr_ref_clk_644,
+              clk_156, rst_156,
               xgmii_tx_dc_arr, xgmii_rx_dc_arr,
               tx_serial_arr, rx_serial_arr);
   END GENERATE;

libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd

@@ -22,14 +22,14 @@
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_phy_10gbase_r_lib;
-LIBRARY ip_arria10_transceiver_pll_156_312_lib;
 LIBRARY ip_arria10_transceiver_pll_10g_lib;
 LIBRARY ip_arria10_transceiver_reset_controller_1_lib;
 
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, tech_pll_lib, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_interface_layers_pkg.ALL;
+USE tech_pll_lib.tech_pll_component_pkg.ALL;
 USE work.tech_10gbase_r_component_pkg.ALL;
 
 ENTITY tech_10gbase_r_arria10 IS
@@ -38,14 +38,12 @@ ENTITY tech_10gbase_r_arria10 IS
     g_nof_channels   : NATURAL := 1
   );
   PORT (
-    -- Transceiver PLL reference clock
-    tr_ref_clk              : IN  STD_LOGIC;    -- 644.531250 MHz
+    -- Transceiver ATX PLL reference clock
+    tr_ref_clk_644          : IN  STD_LOGIC;   -- 644.531250 MHz
     
-    -- Derived clocks
-    clk_312_out             : OUT STD_LOGIC;    -- 312.5 MHz
-    clk_156_out             : OUT STD_LOGIC;    -- 156.25 MHz
-    clk_156_in              : IN  STD_LOGIC;    -- externally connect to clk_156_out to avoid delta-cycle differences in simulation
-    rst_156                 : OUT STD_LOGIC;    -- reset for clk_156_in clock domain
+    -- XGMII clocks
+    clk_156                 : IN STD_LOGIC;    -- 156.25 MHz
+    rst_156                 : IN STD_LOGIC;
 
     -- XGMII interface
     xgmii_tx_dc_arr         : IN  t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0);  -- 72 bit
@@ -62,8 +60,7 @@ ARCHITECTURE str OF tech_10gbase_r_arria10 IS
 
   SIGNAL tx_serial_clk          : STD_LOGIC_VECTOR(0 DOWNTO 0);
 
-  SIGNAL tx_coreclkin           : STD_LOGIC_VECTOR(0 DOWNTO 0);
-  SIGNAL rx_coreclkin           : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL tr_coreclkin           : STD_LOGIC_VECTOR(0 DOWNTO 0);
 
   SIGNAL tx_parallel_data_arr   : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0);  -- 64 bit
   SIGNAL rx_parallel_data_arr   : t_xgmii_d_arr(g_nof_channels-1 DOWNTO 0);  -- 64 bit
@@ -87,28 +84,21 @@ ARCHITECTURE str OF tech_10gbase_r_arria10 IS
   SIGNAL atx_pll_locked         : STD_LOGIC;
   SIGNAL atx_pll_cal_busy       : STD_LOGIC;
   
-  -- transceiver fractional PLL for 156.25 MHz and 312.5 MHz from tr_ref_clk = 644.53125 MHz
-  SIGNAL fpll_cal_busy          : STD_LOGIC;
-  SIGNAL fpll_locked            : STD_LOGIC;
-  SIGNAL fpll_locked_n          : STD_LOGIC;
-  SIGNAL i_rst_156              : STD_LOGIC;
-  
 BEGIN
 
   -- Clocks
-  tx_coreclkin(0) <= clk_156_in;
-  rx_coreclkin(0) <= clk_156_in;
+  tr_coreclkin(0) <= clk_156;
                                 
   gen_phy : FOR I IN 0 TO g_nof_channels-1 GENERATE                                
     -- Reset controller
     cal_busy_arr(I) <= tx_cal_busy_arr(I) OR atx_pll_cal_busy;
     
     -- On hardware use atx_pll_locked for all channels, in simulation model some timing difference between the channels
-    on_hw : IF g_sim=FALSE GENERATE
+    gen_hw : IF g_sim=FALSE GENERATE
       atx_pll_locked_arr(I) <= atx_pll_locked;
     END GENERATE;
-    in_sim : IF g_sim=TRUE GENERATE
-      atx_pll_locked_arr(I) <= TRANSPORT atx_pll_locked AFTER tech_10gbase_r_clk_156_period*I;
+    gen_sim : IF g_sim=TRUE GENERATE
+      atx_pll_locked_arr(I) <= TRANSPORT atx_pll_locked AFTER tech_pll_clk_156_period*I;
     END GENERATE;
     
     -- XGMII
@@ -127,15 +117,15 @@ BEGIN
       rx_cal_busy             => rx_cal_busy_arr(I DOWNTO I),
   
       tx_serial_clk0          => tx_serial_clk,
-      rx_cdr_refclk0          => tr_ref_clk,
+      rx_cdr_refclk0          => tr_ref_clk_644,
       tx_serial_data          => tx_serial_arr(I DOWNTO I),
       rx_serial_data          => rx_serial_arr(I DOWNTO I),
   
       rx_is_lockedtoref       => OPEN,
       rx_is_lockedtodata      => rx_is_lockedtodata_arr(I DOWNTO I),
   
-      tx_coreclkin            => tx_coreclkin,     -- 156.25 MHz
-      rx_coreclkin            => rx_coreclkin,     -- 156.25 MHz
+      tx_coreclkin            => tr_coreclkin,     -- 156.25 MHz
+      rx_coreclkin            => tr_coreclkin,     -- 156.25 MHz
   
       tx_parallel_data        => tx_parallel_data_arr(I),
       rx_parallel_data        => rx_parallel_data_arr(I),
@@ -165,8 +155,8 @@ BEGIN
   
     u_ip_arria10_transceiver_reset_controller_1_top : ip_arria10_transceiver_reset_controller_1_top
     PORT MAP (
-      clock              => clk_156_in,
-      reset              => i_rst_156,
+      clock              => clk_156,
+      reset              => rst_156,
       pll_powerdown      => atx_pll_powerdown(I DOWNTO I),
       tx_analogreset     => tx_analogreset_arr(I DOWNTO I),
       tx_digitalreset    => tx_digitalreset_arr(I DOWNTO I),
@@ -186,36 +176,10 @@ BEGIN
   u_ip_arria10_transceiver_pll_10g_top : ip_arria10_transceiver_pll_10g_top
   PORT MAP (
     pll_powerdown => atx_pll_powerdown(0),
-    pll_refclk0   => tr_ref_clk,
+    pll_refclk0   => tr_ref_clk_644,
     tx_serial_clk => tx_serial_clk(0),
     pll_locked    => atx_pll_locked,
     pll_cal_busy  => atx_pll_cal_busy
   );
     
-  -- fractional PLL
-  u_ip_arria10_transceiver_pll_156_312_top : ip_arria10_transceiver_pll_156_312_top
-  PORT MAP (
-		pll_refclk0   => tr_ref_clk,
-		pll_powerdown => '0',
-		pll_locked    => fpll_locked,
-		outclk0       => clk_156_out,
-		pll_cal_busy  => fpll_cal_busy,
-		outclk1       => clk_312_out
-  );
-  
-  fpll_locked_n <= NOT fpll_locked;
-  
-  u_common_areset : ENTITY common_lib.common_areset
-  GENERIC MAP (
-    g_rst_level => '1',
-    g_delay_len => c_meta_delay_len
-  )
-  PORT MAP (
-    in_rst    => fpll_locked_n,
-    clk       => clk_156_in,
-    out_rst   => i_rst_156
-  );
-  
-  rst_156 <= i_rst_156;
-  
 END str;

libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd

@@ -27,10 +27,6 @@ USE technology_lib.technology_pkg.ALL;
 
 PACKAGE tech_10gbase_r_component_pkg IS
 
-  CONSTANT tech_10gbase_r_ref_clk_period    : TIME := 1551520 fs;                             -- = 1.551520 ns ~= 644.53125 MHz
-  CONSTANT tech_10gbase_r_clk_156_period    : TIME := (tech_10gbase_r_ref_clk_period*33)/8;   -- = 6.400020 ns ~= 156.25 MHz
-  CONSTANT tech_10gbase_r_clk_312_period    : TIME := (tech_10gbase_r_ref_clk_period*33)/16;  -- = 3.200010 ns ~= 312.5 MHz
-
   ------------------------------------------------------------------------------
   -- ip_arria10
   ------------------------------------------------------------------------------
@@ -79,18 +75,6 @@ PACKAGE tech_10gbase_r_component_pkg IS
   );
   END COMPONENT;
 
-  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_156_312/ip_arria10_transceiver_pll_156_312_top.vhd
-  COMPONENT ip_arria10_transceiver_pll_156_312_top IS
-  PORT (
-    pll_refclk0   : in  std_logic := '0'; --   pll_refclk0.clk
-    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
-    pll_locked    : out std_logic;        --    pll_locked.pll_locked
-    outclk0       : out std_logic;        --       outclk0.clk
-    pll_cal_busy  : out std_logic;        --  pll_cal_busy.pll_cal_busy
-    outclk1       : out std_logic         --       outclk1.clk
-  );
-  END COMPONENT;
-  
   -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
   COMPONENT ip_arria10_transceiver_pll_10g_top IS
   PORT (