Added draft version for technology independent tech_10gbase_r for XGMII interface on Arria10.

libraries/technology/10gbase_r/hdllib.cfg

+hdl_lib_name = tech_10gbase_r
+hdl_library_clause_name = tech_10gbase_r_lib
+hdl_lib_uses = technology ip_arria10_phy_10gbase_r ip_arria10_transceiver_pll_10g ip_arria10_transceiver_reset_controller_1 common
+hdl_lib_technology = 
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    tech_10gbase_r_component_pkg.vhd
+    tech_10gbase_r_arria10.vhd
+    tech_10gbase_r.vhd
+
+test_bench_files =
+    tb_tech_10gbase_r.vhd
+
+modelsim_search_libraries =
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip

libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Testbench for tech_10gbase_r.
+-- Description:
+--   The tb is not self checking.
+--   The tb is used to investigate what clocks the 10gbase_r phy uses.
+-- Usage:
+--   > as 10
+--   > run 100 us
+
+LIBRARY IEEE, technology_lib, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+
+ENTITY tb_tech_10gbase_r IS
+  -- Test bench control parameters
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_nof_phy    : NATURAL := 1
+  );
+END tb_tech_10gbase_r;
+
+
+ARCHITECTURE tb OF tb_tech_10gbase_r IS
+
+  CONSTANT sys_clk_period       : TIME :=  5 ns;     -- 200 MHz
+  CONSTANT tr_ref_clk_period    : TIME :=  1551515 fs;  -- ~ 644.53125 MHz
+  CONSTANT tx_core_clk_period   : TIME :=  5 ns; --6.4 ns;   -- 156.25 MHz
+  CONSTANT rx_core_clk_period   : TIME :=  5 ns; --6.4 ns;   -- 156.25 MHz
+  CONSTANT phy_delay            : TIME :=  1 ns;
+  
+  SIGNAL sys_clk                : STD_LOGIC := '0';
+  SIGNAL sys_rst                : STD_LOGIC;
+
+  SIGNAL tr_ref_clk             : STD_LOGIC := '0';
+
+  SIGNAL tx_core_clk_in         : STD_LOGIC := '0';
+  SIGNAL rx_core_clk_in         : STD_LOGIC := '0';
+    
+  SIGNAL tx_pma_div_clk_out     : STD_LOGIC;
+  SIGNAL tx_pma_clk_out         : STD_LOGIC;
+  SIGNAL tx_clk_out             : STD_LOGIC;    -- 156.25 MHz
+  SIGNAL rx_clk_out             : STD_LOGIC;    -- 156.25 MHz
+    
+  -- XGMII interface
+  SIGNAL xgmii_tx_dc_arr   : t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
+  SIGNAL xgmii_rx_dc_arr   : t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
+
+  -- PHY serial interface
+  SIGNAL tx_serial_arr     : STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
+  SIGNAL rx_serial_arr     : STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
+  
+BEGIN
+
+  -- run 50 us
+  sys_clk        <= NOT sys_clk        AFTER sys_clk_period/2;
+  tr_ref_clk     <= NOT tr_ref_clk     AFTER tr_ref_clk_period/2;
+  tx_core_clk_in <= NOT tx_core_clk_in AFTER tx_core_clk_period/2;
+  rx_core_clk_in <= NOT rx_core_clk_in AFTER rx_core_clk_period/2;
+  
+  sys_rst <= '1', '0' AFTER sys_clk_period*10;
+
+  dut : ENTITY work.tech_10gbase_r
+  GENERIC MAP (
+    g_technology          => g_technology,
+    g_nof_phy             => g_nof_phy
+  )
+  PORT MAP (
+    sys_clk                 => sys_clk,
+    sys_rst                 => sys_rst,
+
+    -- Transceiver PLL reference clock
+    tr_ref_clk              => tr_ref_clk,
+
+    tx_core_clk_in          => tx_core_clk_in,
+    rx_core_clk_in          => rx_core_clk_in,
+    
+    tx_pma_div_clk_out      => tx_pma_div_clk_out,
+    tx_pma_clk_out          => tx_pma_clk_out,
+    tx_clk_out              => tx_clk_out,            -- 156.25 MHz
+    rx_clk_out              => rx_clk_out,            -- 156.25 MHz
+    
+    xgmii_tx_dc_arr         => xgmii_tx_dc_arr,
+    xgmii_rx_dc_arr         => xgmii_rx_dc_arr,
+
+    tx_serial_arr           => tx_serial_arr,
+    rx_serial_arr           => rx_serial_arr
+  );
+  
+  -- PHY loopback
+  rx_serial_arr <= TRANSPORT tx_serial_arr AFTER phy_delay;
+  
+END tb;

libraries/technology/10gbase_r/tech_10gbase_r.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+
+ENTITY tech_10gbase_r IS
+  GENERIC (
+    g_technology      : NATURAL := c_tech_select_default;
+    g_nof_phy         : NATURAL := 1
+  );                      
+  PORT (
+    sys_clk                 : IN  STD_LOGIC;    -- 200 MHz
+    sys_rst                 : IN  STD_LOGIC;
+
+    -- Transceiver PLL reference clock
+    tr_ref_clk              : IN  STD_LOGIC;    -- 644.531250 MHz
+
+    tx_core_clk_in          : IN  STD_LOGIC;    -- 156.25 MHz
+    rx_core_clk_in          : IN  STD_LOGIC;    -- 156.25 MHz
+    
+    tx_pma_div_clk_out      : OUT STD_LOGIC;
+    tx_pma_clk_out          : OUT STD_LOGIC;
+    tx_clk_out              : OUT STD_LOGIC;    -- 156.25 MHz
+    rx_clk_out              : OUT STD_LOGIC;    -- 156.25 MHz
+    
+    xgmii_tx_dc_arr         : IN  t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
+    xgmii_rx_dc_arr         : OUT t_xgmii_dc_arr(g_nof_phy-1 DOWNTO 0);
+
+    tx_serial_arr           : OUT STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0);
+    rx_serial_arr           : IN  STD_LOGIC_VECTOR(g_nof_phy-1 DOWNTO 0)
+  );
+END tech_10gbase_r;
+
+
+ARCHITECTURE str OF tech_10gbase_r IS  
+
+BEGIN
+ 
+  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
+    u0 : ENTITY work.tech_10gbase_r_arria10
+    GENERIC MAP (g_nof_phy)
+    PORT MAP (sys_clk, sys_rst,
+              tr_ref_clk, tx_core_clk_in, rx_core_clk_in,
+              tx_pma_div_clk_out, tx_pma_clk_out, tx_clk_out, rx_clk_out,
+              xgmii_tx_dc_arr(0), xgmii_rx_dc_arr(0),
+              tx_serial_arr(0), rx_serial_arr(0));
+  END GENERATE;
+      
+END str;
+

libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd

+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_arria10_phy_10gbase_r_lib;
+LIBRARY ip_arria10_transceiver_pll_10g_lib;
+LIBRARY ip_arria10_transceiver_reset_controller_1_lib;
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE work.tech_10gbase_r_component_pkg.ALL;
+
+ENTITY tech_10gbase_r_arria10 IS
+  GENERIC (
+    g_nof_phy   : NATURAL := 1   -- fixed for now
+  );
+  PORT (
+    sys_clk                 : IN  STD_LOGIC;    -- 200 MHz
+    sys_rst                 : IN  STD_LOGIC;
+
+    -- Transceiver PLL reference clock
+    tr_ref_clk              : IN  STD_LOGIC;    -- 644.531250 MHz
+
+    tx_core_clk_in          : IN  STD_LOGIC;    -- 156.25 MHz
+    rx_core_clk_in          : IN  STD_LOGIC;    -- 156.25 MHz
+    
+    tx_pma_div_clk_out      : OUT STD_LOGIC;
+    tx_pma_clk_out          : OUT STD_LOGIC;
+    tx_clk_out              : OUT STD_LOGIC;    -- 156.25 MHz
+    rx_clk_out              : OUT STD_LOGIC;    -- 156.25 MHz
+
+    -- XGMII interface
+    xgmii_tx_dc             : IN  STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);  -- 72 bit
+    xgmii_rx_dc             : OUT STD_LOGIC_VECTOR(c_xgmii_w-1 DOWNTO 0);  -- 72 bit
+
+    -- PHY serial IO
+    tx_serial               : OUT STD_LOGIC;
+    rx_serial               : IN  STD_LOGIC
+  );
+END tech_10gbase_r_arria10;
+
+
+ARCHITECTURE str OF tech_10gbase_r_arria10 IS
+
+  SIGNAL tx_serial_clk     : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL tx_serial_data    : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL rx_serial_data    : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+  SIGNAL tx_coreclkin      : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL rx_coreclkin      : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+  SIGNAL tx_pma_div_clkout : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL tx_pma_clkout     : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL tx_clkout         : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL rx_clkout         : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+  SIGNAL tx_parallel_data  : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0);  -- 64 bit
+  SIGNAL rx_parallel_data  : STD_LOGIC_VECTOR(c_xgmii_data_w-1 DOWNTO 0);  -- 64 bit
+  SIGNAL tx_control        : STD_LOGIC_VECTOR(c_xgmii_ctrl_w-1 DOWNTO 0);  --  8 bit
+  SIGNAL rx_control        : STD_LOGIC_VECTOR(c_xgmii_ctrl_w-1 DOWNTO 0);  --  8 bit
+
+  -- transceiver reset controller
+  SIGNAL tx_analogreset     : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL tx_digitalreset    : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL rx_analogreset     : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL rx_digitalreset    : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL tx_cal_busy        : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL rx_cal_busy        : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL rx_is_lockedtodata : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+  SIGNAL pll_or_tx_cal_busy : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+  -- transceiver PLL for 10G
+  SIGNAL pll_powerdown      : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL pll_locked         : STD_LOGIC_VECTOR(0 DOWNTO 0);
+  SIGNAL pll_cal_busy       : STD_LOGIC;
+
+BEGIN
+
+  -- Clocks
+  tx_coreclkin(0)    <= tx_core_clk_in;
+  rx_coreclkin(0)    <= rx_core_clk_in;
+  
+  tx_clk_out         <= tx_clkout(0);
+  rx_clk_out         <= rx_clkout(0);
+
+  tx_pma_div_clk_out <= tx_pma_div_clkout(0);
+  tx_pma_clk_out     <= tx_pma_clkout(0);
+
+  -- Serial
+  tx_serial          <= tx_serial_data(0);
+  rx_serial_data(0)  <= rx_serial;
+
+  -- Reset controller
+  pll_or_tx_cal_busy(0) <= tx_cal_busy(0) OR pll_cal_busy;
+  
+  -- XGMII
+  tx_parallel_data(63 DOWNTO 56) <= xgmii_tx_dc(70 DOWNTO 63);  tx_control(7) <= xgmii_tx_dc(71);
+  tx_parallel_data(55 DOWNTO 48) <= xgmii_tx_dc(61 DOWNTO 54);  tx_control(6) <= xgmii_tx_dc(62);
+  tx_parallel_data(47 DOWNTO 40) <= xgmii_tx_dc(52 DOWNTO 45);  tx_control(5) <= xgmii_tx_dc(53);
+  tx_parallel_data(39 DOWNTO 32) <= xgmii_tx_dc(43 DOWNTO 36);  tx_control(4) <= xgmii_tx_dc(44);
+  tx_parallel_data(31 DOWNTO 24) <= xgmii_tx_dc(34 DOWNTO 27);  tx_control(3) <= xgmii_tx_dc(35);
+  tx_parallel_data(23 DOWNTO 16) <= xgmii_tx_dc(25 DOWNTO 18);  tx_control(2) <= xgmii_tx_dc(26);
+  tx_parallel_data(15 DOWNTO  8) <= xgmii_tx_dc(16 DOWNTO  9);  tx_control(1) <= xgmii_tx_dc(17);
+  tx_parallel_data( 7 DOWNTO  0) <= xgmii_tx_dc( 7 DOWNTO  0);  tx_control(0) <= xgmii_tx_dc( 8);
+
+  xgmii_rx_dc(70 DOWNTO 63) <= rx_parallel_data(63 DOWNTO 56);  xgmii_rx_dc(71) <= rx_control(7);
+  xgmii_rx_dc(61 DOWNTO 54) <= rx_parallel_data(55 DOWNTO 48);  xgmii_rx_dc(62) <= rx_control(6);
+  xgmii_rx_dc(52 DOWNTO 45) <= rx_parallel_data(47 DOWNTO 40);  xgmii_rx_dc(53) <= rx_control(5);
+  xgmii_rx_dc(43 DOWNTO 36) <= rx_parallel_data(39 DOWNTO 32);  xgmii_rx_dc(44) <= rx_control(4);
+  xgmii_rx_dc(34 DOWNTO 27) <= rx_parallel_data(31 DOWNTO 24);  xgmii_rx_dc(35) <= rx_control(3);
+  xgmii_rx_dc(25 DOWNTO 18) <= rx_parallel_data(23 DOWNTO 16);  xgmii_rx_dc(26) <= rx_control(2);
+  xgmii_rx_dc(16 DOWNTO  9) <= rx_parallel_data(15 DOWNTO  8);  xgmii_rx_dc(17) <= rx_control(1);
+  xgmii_rx_dc( 7 DOWNTO  0) <= rx_parallel_data( 7 DOWNTO  0);  xgmii_rx_dc( 8) <= rx_control(0);
+
+
+  u_ip_arria10_phy_10gbase_r_top : ip_arria10_phy_10gbase_r_top
+  PORT MAP (
+    tx_analogreset          => tx_analogreset,
+    tx_digitalreset         => tx_digitalreset,
+    rx_analogreset          => rx_analogreset,
+    rx_digitalreset         => rx_digitalreset,
+    tx_cal_busy             => tx_cal_busy,
+    rx_cal_busy             => rx_cal_busy,
+
+    tx_serial_clk0          => tx_serial_clk,
+    rx_cdr_refclk0          => tr_ref_clk,
+    tx_serial_data          => tx_serial_data,
+    rx_serial_data          => rx_serial_data,
+
+    rx_is_lockedtoref       => OPEN,
+    rx_is_lockedtodata      => rx_is_lockedtodata,
+
+    tx_coreclkin            => tx_coreclkin,
+    rx_coreclkin            => rx_coreclkin,
+    tx_clkout               => tx_clkout,
+    rx_clkout               => rx_clkout,
+
+    tx_parallel_data        => tx_parallel_data,
+    rx_parallel_data        => rx_parallel_data,
+    tx_pma_div_clkout       => tx_pma_div_clkout,
+    tx_control              => tx_control,
+
+    --tx_err_ins              : in  std_logic                     := '0';             --              tx_err_ins.tx_err_ins
+    --unused_tx_parallel_data : in  std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
+    --unused_tx_control       : in  std_logic_vector(8 downto 0)  := (others => '0'); --       unused_tx_control.unused_tx_control
+
+    rx_control              => rx_control,
+
+    --unused_rx_parallel_data : out std_logic_vector(63 downto 0);                    -- unused_rx_parallel_data.unused_rx_parallel_data
+    --unused_rx_control       : out std_logic_vector(11 downto 0);                    --       unused_rx_control.unused_rx_control
+    --tx_enh_data_valid       : in  std_logic_vector(0 downto 0)  := (others => '0'); --       tx_enh_data_valid.tx_enh_data_valid
+    --tx_enh_fifo_full        : out std_logic_vector(0 downto 0);                     --        tx_enh_fifo_full.tx_enh_fifo_full
+    --tx_enh_fifo_pfull       : out std_logic_vector(0 downto 0);                     --       tx_enh_fifo_pfull.tx_enh_fifo_pfull
+    --tx_enh_fifo_empty       : out std_logic_vector(0 downto 0);                     --       tx_enh_fifo_empty.tx_enh_fifo_empty
+    --tx_enh_fifo_pempty      : out std_logic_vector(0 downto 0);                     --      tx_enh_fifo_pempty.tx_enh_fifo_pempty
+    --rx_enh_data_valid       : out std_logic_vector(0 downto 0);                     --       rx_enh_data_valid.rx_enh_data_valid
+    --rx_enh_fifo_full        : out std_logic_vector(0 downto 0);                     --        rx_enh_fifo_full.rx_enh_fifo_full
+    --rx_enh_fifo_empty       : out std_logic_vector(0 downto 0);                     --       rx_enh_fifo_empty.rx_enh_fifo_empty
+    --rx_enh_fifo_del         : out std_logic_vector(0 downto 0);                     --         rx_enh_fifo_del.rx_enh_fifo_del
+    --rx_enh_fifo_insert      : out std_logic_vector(0 downto 0);                     --      rx_enh_fifo_insert.rx_enh_fifo_insert
+    --rx_enh_highber          : out std_logic_vector(0 downto 0);                     --          rx_enh_highber.rx_enh_highber
+    --rx_enh_blk_lock         : out std_logic_vector(0 downto 0);                     --         rx_enh_blk_lock.rx_enh_blk_lock
+
+    tx_pma_clkout           => tx_pma_clkout
+  );
+
+  u_ip_arria10_transceiver_reset_controller_1_top : ip_arria10_transceiver_reset_controller_1_top
+  PORT MAP (
+    clock              => sys_clk,
+    reset              => sys_rst,
+    pll_powerdown      => pll_powerdown,
+    tx_analogreset     => tx_analogreset,
+    tx_digitalreset    => tx_digitalreset,
+    tx_ready           => OPEN,
+    pll_locked         => pll_locked,
+    pll_select         => "0",                   -- set to zero when using one PLL
+    tx_cal_busy        => pll_or_tx_cal_busy,
+    rx_analogreset     => rx_analogreset,
+    rx_digitalreset    => rx_digitalreset,
+    rx_ready           => OPEN,
+    rx_is_lockedtodata => rx_is_lockedtodata,
+    rx_cal_busy        => rx_cal_busy
+  );
+
+  u_ip_arria10_transceiver_pll_10g_top : ip_arria10_transceiver_pll_10g_top
+  PORT MAP (
+    pll_powerdown => pll_powerdown(0),
+    pll_refclk0   => tr_ref_clk,
+    tx_serial_clk => tx_serial_clk(0),
+    pll_locked    => pll_locked(0),
+    pll_cal_busy  => pll_cal_busy
+  );
+  
+END str;

libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: IP components declarations for various devices that get wrapped by the tech components
+
+LIBRARY IEEE, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+PACKAGE tech_10gbase_r_component_pkg IS
+
+  ------------------------------------------------------------------------------
+  -- ip_arria10
+  ------------------------------------------------------------------------------
+  
+  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd
+  COMPONENT ip_arria10_phy_10gbase_r_top IS
+  PORT (
+    tx_analogreset          : in  std_logic_vector(0 downto 0)  := (others => '0'); --          tx_analogreset.tx_analogreset
+    tx_digitalreset         : in  std_logic_vector(0 downto 0)  := (others => '0'); --         tx_digitalreset.tx_digitalreset
+    rx_analogreset          : in  std_logic_vector(0 downto 0)  := (others => '0'); --          rx_analogreset.rx_analogreset
+    rx_digitalreset         : in  std_logic_vector(0 downto 0)  := (others => '0'); --         rx_digitalreset.rx_digitalreset
+    tx_cal_busy             : out std_logic_vector(0 downto 0);                     --             tx_cal_busy.tx_cal_busy
+    rx_cal_busy             : out std_logic_vector(0 downto 0);                     --             rx_cal_busy.rx_cal_busy
+    tx_serial_clk0          : in  std_logic_vector(0 downto 0)  := (others => '0'); --          tx_serial_clk0.clk
+    rx_cdr_refclk0          : in  std_logic                     := '0';             --          rx_cdr_refclk0.clk
+    tx_serial_data          : out std_logic_vector(0 downto 0);                     --          tx_serial_data.tx_serial_data
+    rx_serial_data          : in  std_logic_vector(0 downto 0)  := (others => '0'); --          rx_serial_data.rx_serial_data
+    rx_is_lockedtoref       : out std_logic_vector(0 downto 0);                     --       rx_is_lockedtoref.rx_is_lockedtoref
+    rx_is_lockedtodata      : out std_logic_vector(0 downto 0);                     --      rx_is_lockedtodata.rx_is_lockedtodata
+    tx_coreclkin            : in  std_logic_vector(0 downto 0)  := (others => '0'); --            tx_coreclkin.clk
+    rx_coreclkin            : in  std_logic_vector(0 downto 0)  := (others => '0'); --            rx_coreclkin.clk
+    tx_clkout               : out std_logic_vector(0 downto 0);                     --               tx_clkout.clk
+    rx_clkout               : out std_logic_vector(0 downto 0);                     --               rx_clkout.clk
+    tx_parallel_data        : in  std_logic_vector(63 downto 0) := (others => '0'); --        tx_parallel_data.tx_parallel_data
+    rx_parallel_data        : out std_logic_vector(63 downto 0);                    --        rx_parallel_data.rx_parallel_data
+    tx_pma_div_clkout       : out std_logic_vector(0 downto 0);                     --       tx_pma_div_clkout.clk
+    tx_control              : in  std_logic_vector(7 downto 0)  := (others => '0'); --              tx_control.tx_control
+    tx_err_ins              : in  std_logic                     := '0';             --              tx_err_ins.tx_err_ins
+    unused_tx_parallel_data : in  std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
+    unused_tx_control       : in  std_logic_vector(8 downto 0)  := (others => '0'); --       unused_tx_control.unused_tx_control
+    rx_control              : out std_logic_vector(7 downto 0);                     --              rx_control.rx_control
+    unused_rx_parallel_data : out std_logic_vector(63 downto 0);                    -- unused_rx_parallel_data.unused_rx_parallel_data
+    unused_rx_control       : out std_logic_vector(11 downto 0);                    --       unused_rx_control.unused_rx_control
+    tx_enh_data_valid       : in  std_logic_vector(0 downto 0)  := (others => '0'); --       tx_enh_data_valid.tx_enh_data_valid
+    tx_enh_fifo_full        : out std_logic_vector(0 downto 0);                     --        tx_enh_fifo_full.tx_enh_fifo_full
+    tx_enh_fifo_pfull       : out std_logic_vector(0 downto 0);                     --       tx_enh_fifo_pfull.tx_enh_fifo_pfull
+    tx_enh_fifo_empty       : out std_logic_vector(0 downto 0);                     --       tx_enh_fifo_empty.tx_enh_fifo_empty
+    tx_enh_fifo_pempty      : out std_logic_vector(0 downto 0);                     --      tx_enh_fifo_pempty.tx_enh_fifo_pempty
+    rx_enh_data_valid       : out std_logic_vector(0 downto 0);                     --       rx_enh_data_valid.rx_enh_data_valid
+    rx_enh_fifo_full        : out std_logic_vector(0 downto 0);                     --        rx_enh_fifo_full.rx_enh_fifo_full
+    rx_enh_fifo_empty       : out std_logic_vector(0 downto 0);                     --       rx_enh_fifo_empty.rx_enh_fifo_empty
+    rx_enh_fifo_del         : out std_logic_vector(0 downto 0);                     --         rx_enh_fifo_del.rx_enh_fifo_del
+    rx_enh_fifo_insert      : out std_logic_vector(0 downto 0);                     --      rx_enh_fifo_insert.rx_enh_fifo_insert
+    rx_enh_highber          : out std_logic_vector(0 downto 0);                     --          rx_enh_highber.rx_enh_highber
+    rx_enh_blk_lock         : out std_logic_vector(0 downto 0);                     --         rx_enh_blk_lock.rx_enh_blk_lock
+    tx_pma_clkout           : out std_logic_vector(0 downto 0)                      --           tx_pma_clkout.clk
+  );
+  END COMPONENT;
+
+  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
+  COMPONENT ip_arria10_transceiver_pll_10g_top IS
+  PORT (
+    pll_powerdown : in  std_logic := '0'; -- pll_powerdown.pll_powerdown
+    pll_refclk0   : in  std_logic := '0'; --   pll_refclk0.clk
+    tx_serial_clk : out std_logic;        -- tx_serial_clk.clk
+    pll_locked    : out std_logic;        --    pll_locked.pll_locked
+    pll_cal_busy  : out std_logic         --  pll_cal_busy.pll_cal_busy
+  );
+  END COMPONENT;
+
+  -- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1_top.vhd
+  COMPONENT ip_arria10_transceiver_reset_controller_1_top IS
+  PORT (
+    clock              : in  std_logic                    := '0';             --              clock.clk
+    reset              : in  std_logic                    := '0';             --              reset.reset
+    pll_powerdown      : out std_logic_vector(0 downto 0);                    --      pll_powerdown.pll_powerdown
+    tx_analogreset     : out std_logic_vector(0 downto 0);                    --     tx_analogreset.tx_analogreset
+    tx_digitalreset    : out std_logic_vector(0 downto 0);                    --    tx_digitalreset.tx_digitalreset
+    tx_ready           : out std_logic_vector(0 downto 0);                    --           tx_ready.tx_ready
+    pll_locked         : in  std_logic_vector(0 downto 0) := (others => '0'); --         pll_locked.pll_locked
+    pll_select         : in  std_logic_vector(0 downto 0) := (others => '0'); --         pll_select.pll_select
+    tx_cal_busy        : in  std_logic_vector(0 downto 0) := (others => '0'); --        tx_cal_busy.tx_cal_busy
+    rx_analogreset     : out std_logic_vector(0 downto 0);                    --     rx_analogreset.rx_analogreset
+    rx_digitalreset    : out std_logic_vector(0 downto 0);                    --    rx_digitalreset.rx_digitalreset
+    rx_ready           : out std_logic_vector(0 downto 0);                    --           rx_ready.rx_ready
+    rx_is_lockedtodata : in  std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
+    rx_cal_busy        : in  std_logic_vector(0 downto 0) := (others => '0')  --        rx_cal_busy.rx_cal_busy
+  );
+  END COMPONENT;
+  
+END tech_10gbase_r_component_pkg;