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Commit 5e2a3e00 authored by Eric Kooistra's avatar Eric Kooistra
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Added missing r-6, r-9 items in tech_10gbase_r_component_pkg.vhd and... 

Added missing r-6, r-9 items in tech_10gbase_r_component_pkg.vhd and ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
parent 94041550
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......@@ -127,114 +127,6 @@ package tech_10gbase_r_component_pkg is
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_6
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
rx_analogreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(5 downto 0); -- rx_cal_busy
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
rx_clkout : out std_logic_vector(5 downto 0); -- clk
rx_control : out std_logic_vector(47 downto 0); -- rx_control
rx_coreclkin : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
rx_digitalreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(5 downto 0); -- rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(5 downto 0); -- rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(5 downto 0); -- rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(5 downto 0); -- rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(5 downto 0); -- rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(5 downto 0); -- rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(5 downto 0); -- rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(5 downto 0); -- rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(5 downto 0); -- rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(383 downto 0); -- rx_parallel_data
rx_prbs_done : out std_logic_vector(5 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(5 downto 0); -- rx_prbs_err
rx_prbs_err_clr : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_prbs_err_clr
rx_serial_data : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_serial_data
rx_seriallpbken : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_seriallpbken
tx_analogreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(5 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(5 downto 0); -- clk
tx_control : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_control
tx_coreclkin : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
tx_digitalreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_digitalreset
tx_enh_data_valid : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(5 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(5 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(5 downto 0); -- tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(5 downto 0); -- tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_err_ins
tx_parallel_data : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_parallel_data
tx_serial_clk0 : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(5 downto 0); -- tx_serial_data
unused_rx_control : out std_logic_vector(71 downto 0); -- unused_rx_control
unused_rx_parallel_data : out std_logic_vector(383 downto 0); -- unused_rx_parallel_data
unused_tx_control : in std_logic_vector(53 downto 0) := (others => 'X'); -- unused_tx_control
unused_tx_parallel_data : in std_logic_vector(383 downto 0) := (others => 'X') -- unused_tx_parallel_data
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_9
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
rx_analogreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(8 downto 0); -- rx_cal_busy
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
rx_clkout : out std_logic_vector(8 downto 0); -- clk
rx_control : out std_logic_vector(71 downto 0); -- rx_control
rx_coreclkin : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
rx_digitalreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(8 downto 0); -- rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(8 downto 0); -- rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(8 downto 0); -- rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(8 downto 0); -- rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(8 downto 0); -- rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(8 downto 0); -- rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(8 downto 0); -- rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(8 downto 0); -- rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(8 downto 0); -- rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(575 downto 0); -- rx_parallel_data
rx_prbs_done : out std_logic_vector(8 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(8 downto 0); -- rx_prbs_err
rx_prbs_err_clr : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_prbs_err_clr
rx_serial_data : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_serial_data
rx_seriallpbken : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_seriallpbken
tx_analogreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(8 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(8 downto 0); -- clk
tx_control : in std_logic_vector(71 downto 0) := (others => 'X'); -- tx_control
tx_coreclkin : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
tx_digitalreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_digitalreset
tx_enh_data_valid : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(8 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(8 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(8 downto 0); -- tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(8 downto 0); -- tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_err_ins
tx_parallel_data : in std_logic_vector(575 downto 0) := (others => 'X'); -- tx_parallel_data
tx_serial_clk0 : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(8 downto 0); -- tx_serial_data
unused_rx_control : out std_logic_vector(107 downto 0); -- unused_rx_control
unused_rx_parallel_data : out std_logic_vector(575 downto 0); -- unused_rx_parallel_data
unused_tx_control : in std_logic_vector(80 downto 0) := (others => 'X'); -- unused_tx_control
unused_tx_parallel_data : in std_logic_vector(575 downto 0) := (others => 'X') -- unused_tx_parallel_data
);
end component;
component ip_arria10_phy_10gbase_r_12
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
......@@ -462,44 +354,6 @@ package tech_10gbase_r_component_pkg is
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_6
port (
clock : in std_logic := 'X'; -- clk
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
reset : in std_logic := 'X'; -- reset
rx_analogreset : out std_logic_vector(5 downto 0); -- rx_analogreset
rx_cal_busy : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_cal_busy
rx_digitalreset : out std_logic_vector(5 downto 0); -- rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_ready : out std_logic_vector(5 downto 0); -- rx_ready
tx_analogreset : out std_logic_vector(5 downto 0); -- tx_analogreset
tx_cal_busy : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_cal_busy
tx_digitalreset : out std_logic_vector(5 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(5 downto 0) -- tx_ready
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_9
port (
clock : in std_logic := 'X'; -- clk
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
reset : in std_logic := 'X'; -- reset
rx_analogreset : out std_logic_vector(8 downto 0); -- rx_analogreset
rx_cal_busy : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_cal_busy
rx_digitalreset : out std_logic_vector(8 downto 0); -- rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_ready : out std_logic_vector(8 downto 0); -- rx_ready
tx_analogreset : out std_logic_vector(8 downto 0); -- tx_analogreset
tx_cal_busy : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_cal_busy
tx_digitalreset : out std_logic_vector(8 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(8 downto 0) -- tx_ready
);
end component;
component ip_arria10_transceiver_reset_controller_12
port (
clock : in std_logic := '0'; -- clock.clk
......@@ -1099,6 +953,114 @@ package tech_10gbase_r_component_pkg is
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_6
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
rx_analogreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(5 downto 0); -- rx_cal_busy
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
rx_clkout : out std_logic_vector(5 downto 0); -- clk
rx_control : out std_logic_vector(47 downto 0); -- rx_control
rx_coreclkin : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
rx_digitalreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(5 downto 0); -- rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(5 downto 0); -- rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(5 downto 0); -- rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(5 downto 0); -- rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(5 downto 0); -- rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(5 downto 0); -- rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(5 downto 0); -- rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(5 downto 0); -- rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(5 downto 0); -- rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(383 downto 0); -- rx_parallel_data
rx_prbs_done : out std_logic_vector(5 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(5 downto 0); -- rx_prbs_err
rx_prbs_err_clr : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_prbs_err_clr
rx_serial_data : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_serial_data
rx_seriallpbken : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_seriallpbken
tx_analogreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(5 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(5 downto 0); -- clk
tx_control : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_control
tx_coreclkin : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
tx_digitalreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_digitalreset
tx_enh_data_valid : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(5 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(5 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(5 downto 0); -- tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(5 downto 0); -- tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_err_ins
tx_parallel_data : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_parallel_data
tx_serial_clk0 : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(5 downto 0); -- tx_serial_data
unused_rx_control : out std_logic_vector(71 downto 0); -- unused_rx_control
unused_rx_parallel_data : out std_logic_vector(383 downto 0); -- unused_rx_parallel_data
unused_tx_control : in std_logic_vector(53 downto 0) := (others => 'X'); -- unused_tx_control
unused_tx_parallel_data : in std_logic_vector(383 downto 0) := (others => 'X') -- unused_tx_parallel_data
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_9
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0); -- waitrequest
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
rx_analogreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_analogreset
rx_cal_busy : out std_logic_vector(8 downto 0); -- rx_cal_busy
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
rx_clkout : out std_logic_vector(8 downto 0); -- clk
rx_control : out std_logic_vector(71 downto 0); -- rx_control
rx_coreclkin : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
rx_digitalreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_digitalreset
rx_enh_blk_lock : out std_logic_vector(8 downto 0); -- rx_enh_blk_lock
rx_enh_data_valid : out std_logic_vector(8 downto 0); -- rx_enh_data_valid
rx_enh_fifo_del : out std_logic_vector(8 downto 0); -- rx_enh_fifo_del
rx_enh_fifo_empty : out std_logic_vector(8 downto 0); -- rx_enh_fifo_empty
rx_enh_fifo_full : out std_logic_vector(8 downto 0); -- rx_enh_fifo_full
rx_enh_fifo_insert : out std_logic_vector(8 downto 0); -- rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(8 downto 0); -- rx_enh_highber
rx_is_lockedtodata : out std_logic_vector(8 downto 0); -- rx_is_lockedtodata
rx_is_lockedtoref : out std_logic_vector(8 downto 0); -- rx_is_lockedtoref
rx_parallel_data : out std_logic_vector(575 downto 0); -- rx_parallel_data
rx_prbs_done : out std_logic_vector(8 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(8 downto 0); -- rx_prbs_err
rx_prbs_err_clr : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_prbs_err_clr
rx_serial_data : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_serial_data
rx_seriallpbken : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_seriallpbken
tx_analogreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_analogreset
tx_cal_busy : out std_logic_vector(8 downto 0); -- tx_cal_busy
tx_clkout : out std_logic_vector(8 downto 0); -- clk
tx_control : in std_logic_vector(71 downto 0) := (others => 'X'); -- tx_control
tx_coreclkin : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
tx_digitalreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_digitalreset
tx_enh_data_valid : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_enh_data_valid
tx_enh_fifo_empty : out std_logic_vector(8 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_full : out std_logic_vector(8 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pempty : out std_logic_vector(8 downto 0); -- tx_enh_fifo_pempty
tx_enh_fifo_pfull : out std_logic_vector(8 downto 0); -- tx_enh_fifo_pfull
tx_err_ins : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_err_ins
tx_parallel_data : in std_logic_vector(575 downto 0) := (others => 'X'); -- tx_parallel_data
tx_serial_clk0 : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
tx_serial_data : out std_logic_vector(8 downto 0); -- tx_serial_data
unused_rx_control : out std_logic_vector(107 downto 0); -- unused_rx_control
unused_rx_parallel_data : out std_logic_vector(575 downto 0); -- unused_rx_parallel_data
unused_tx_control : in std_logic_vector(80 downto 0) := (others => 'X'); -- unused_tx_control
unused_tx_parallel_data : in std_logic_vector(575 downto 0) := (others => 'X') -- unused_tx_parallel_data
);
end component;
component ip_arria10_e1sg_phy_10gbase_r_12
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
......@@ -1344,6 +1306,44 @@ package tech_10gbase_r_component_pkg is
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_6
port (
clock : in std_logic := 'X'; -- clk
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
reset : in std_logic := 'X'; -- reset
rx_analogreset : out std_logic_vector(5 downto 0); -- rx_analogreset
rx_cal_busy : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_cal_busy
rx_digitalreset : out std_logic_vector(5 downto 0); -- rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_ready : out std_logic_vector(5 downto 0); -- rx_ready
tx_analogreset : out std_logic_vector(5 downto 0); -- tx_analogreset
tx_cal_busy : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_cal_busy
tx_digitalreset : out std_logic_vector(5 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(5 downto 0) -- tx_ready
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_9
port (
clock : in std_logic := 'X'; -- clk
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
reset : in std_logic := 'X'; -- reset
rx_analogreset : out std_logic_vector(8 downto 0); -- rx_analogreset
rx_cal_busy : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_cal_busy
rx_digitalreset : out std_logic_vector(8 downto 0); -- rx_digitalreset
rx_is_lockedtodata : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_ready : out std_logic_vector(8 downto 0); -- rx_ready
tx_analogreset : out std_logic_vector(8 downto 0); -- tx_analogreset
tx_cal_busy : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_cal_busy
tx_digitalreset : out std_logic_vector(8 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(8 downto 0) -- tx_ready
);
end component;
component ip_arria10_e1sg_transceiver_reset_controller_12
port (
clock : in std_logic := '0'; -- clock.clk
......@@ -1559,6 +1559,114 @@ package tech_10gbase_r_component_pkg is
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_6
port (
tx_analogreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_analogreset
tx_digitalreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_digitalreset
rx_analogreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_analogreset
rx_digitalreset : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_digitalreset
tx_cal_busy : out std_logic_vector(5 downto 0); -- tx_cal_busy
rx_cal_busy : out std_logic_vector(5 downto 0); -- rx_cal_busy
tx_serial_clk0 : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
tx_serial_data : out std_logic_vector(5 downto 0); -- tx_serial_data
rx_serial_data : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_serial_data
rx_seriallpbken : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_seriallpbken
rx_is_lockedtoref : out std_logic_vector(5 downto 0); -- rx_is_lockedtoref
rx_is_lockedtodata : out std_logic_vector(5 downto 0); -- rx_is_lockedtodata
tx_coreclkin : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
rx_coreclkin : in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
tx_clkout : out std_logic_vector(5 downto 0); -- clk
rx_clkout : out std_logic_vector(5 downto 0); -- clk
tx_parallel_data : in std_logic_vector(383 downto 0) := (others => 'X'); -- tx_parallel_data
tx_control : in std_logic_vector(47 downto 0) := (others => 'X'); -- tx_control
tx_err_ins : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_err_ins
unused_tx_parallel_data : in std_logic_vector(383 downto 0) := (others => 'X'); -- unused_tx_parallel_data
unused_tx_control : in std_logic_vector(53 downto 0) := (others => 'X'); -- unused_tx_control
rx_parallel_data : out std_logic_vector(383 downto 0); -- rx_parallel_data
rx_control : out std_logic_vector(47 downto 0); -- rx_control
unused_rx_parallel_data : out std_logic_vector(383 downto 0); -- unused_rx_parallel_data
unused_rx_control : out std_logic_vector(71 downto 0); -- unused_rx_control
rx_prbs_err_clr : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_prbs_err_clr
rx_prbs_done : out std_logic_vector(5 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(5 downto 0); -- rx_prbs_err
tx_enh_data_valid : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_enh_data_valid
tx_enh_fifo_full : out std_logic_vector(5 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pfull : out std_logic_vector(5 downto 0); -- tx_enh_fifo_pfull
tx_enh_fifo_empty : out std_logic_vector(5 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_pempty : out std_logic_vector(5 downto 0); -- tx_enh_fifo_pempty
rx_enh_data_valid : out std_logic_vector(5 downto 0); -- rx_enh_data_valid
rx_enh_fifo_full : out std_logic_vector(5 downto 0); -- rx_enh_fifo_full
rx_enh_fifo_empty : out std_logic_vector(5 downto 0); -- rx_enh_fifo_empty
rx_enh_fifo_del : out std_logic_vector(5 downto 0); -- rx_enh_fifo_del
rx_enh_fifo_insert : out std_logic_vector(5 downto 0); -- rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(5 downto 0); -- rx_enh_highber
rx_enh_blk_lock : out std_logic_vector(5 downto 0); -- rx_enh_blk_lock
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(12 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0) -- waitrequest
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_9
port (
tx_analogreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_analogreset
tx_digitalreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_digitalreset
rx_analogreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_analogreset
rx_digitalreset : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_digitalreset
tx_cal_busy : out std_logic_vector(8 downto 0); -- tx_cal_busy
rx_cal_busy : out std_logic_vector(8 downto 0); -- rx_cal_busy
tx_serial_clk0 : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
rx_cdr_refclk0 : in std_logic := 'X'; -- clk
tx_serial_data : out std_logic_vector(8 downto 0); -- tx_serial_data
rx_serial_data : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_serial_data
rx_seriallpbken : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_seriallpbken
rx_is_lockedtoref : out std_logic_vector(8 downto 0); -- rx_is_lockedtoref
rx_is_lockedtodata : out std_logic_vector(8 downto 0); -- rx_is_lockedtodata
tx_coreclkin : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
rx_coreclkin : in std_logic_vector(8 downto 0) := (others => 'X'); -- clk
tx_clkout : out std_logic_vector(8 downto 0); -- clk
rx_clkout : out std_logic_vector(8 downto 0); -- clk
tx_parallel_data : in std_logic_vector(575 downto 0) := (others => 'X'); -- tx_parallel_data
tx_control : in std_logic_vector(71 downto 0) := (others => 'X'); -- tx_control
tx_err_ins : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_err_ins
unused_tx_parallel_data : in std_logic_vector(575 downto 0) := (others => 'X'); -- unused_tx_parallel_data
unused_tx_control : in std_logic_vector(80 downto 0) := (others => 'X'); -- unused_tx_control
rx_parallel_data : out std_logic_vector(575 downto 0); -- rx_parallel_data
rx_control : out std_logic_vector(71 downto 0); -- rx_control
unused_rx_parallel_data : out std_logic_vector(575 downto 0); -- unused_rx_parallel_data
unused_rx_control : out std_logic_vector(107 downto 0); -- unused_rx_control
rx_prbs_err_clr : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_prbs_err_clr
rx_prbs_done : out std_logic_vector(8 downto 0); -- rx_prbs_done
rx_prbs_err : out std_logic_vector(8 downto 0); -- rx_prbs_err
tx_enh_data_valid : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_enh_data_valid
tx_enh_fifo_full : out std_logic_vector(8 downto 0); -- tx_enh_fifo_full
tx_enh_fifo_pfull : out std_logic_vector(8 downto 0); -- tx_enh_fifo_pfull
tx_enh_fifo_empty : out std_logic_vector(8 downto 0); -- tx_enh_fifo_empty
tx_enh_fifo_pempty : out std_logic_vector(8 downto 0); -- tx_enh_fifo_pempty
rx_enh_data_valid : out std_logic_vector(8 downto 0); -- rx_enh_data_valid
rx_enh_fifo_full : out std_logic_vector(8 downto 0); -- rx_enh_fifo_full
rx_enh_fifo_empty : out std_logic_vector(8 downto 0); -- rx_enh_fifo_empty
rx_enh_fifo_del : out std_logic_vector(8 downto 0); -- rx_enh_fifo_del
rx_enh_fifo_insert : out std_logic_vector(8 downto 0); -- rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(8 downto 0); -- rx_enh_highber
rx_enh_blk_lock : out std_logic_vector(8 downto 0); -- rx_enh_blk_lock
reconfig_clk : in std_logic_vector(0 downto 0) := (others => 'X'); -- clk
reconfig_reset : in std_logic_vector(0 downto 0) := (others => 'X'); -- reset
reconfig_write : in std_logic_vector(0 downto 0) := (others => 'X'); -- write
reconfig_read : in std_logic_vector(0 downto 0) := (others => 'X'); -- read
reconfig_address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
reconfig_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
reconfig_readdata : out std_logic_vector(31 downto 0); -- readdata
reconfig_waitrequest : out std_logic_vector(0 downto 0) -- waitrequest
);
end component;
component ip_arria10_e2sg_phy_10gbase_r_12
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
......@@ -1804,6 +1912,44 @@ package tech_10gbase_r_component_pkg is
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_6
port (
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
tx_analogreset : out std_logic_vector(5 downto 0); -- tx_analogreset
tx_digitalreset : out std_logic_vector(5 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(5 downto 0); -- tx_ready
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
tx_cal_busy : in std_logic_vector(5 downto 0) := (others => 'X'); -- tx_cal_busy
rx_analogreset : out std_logic_vector(5 downto 0); -- rx_analogreset
rx_digitalreset : out std_logic_vector(5 downto 0); -- rx_digitalreset
rx_ready : out std_logic_vector(5 downto 0); -- rx_ready
rx_is_lockedtodata : in std_logic_vector(5 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_cal_busy : in std_logic_vector(5 downto 0) := (others => 'X') -- rx_cal_busy
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_9
port (
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
tx_analogreset : out std_logic_vector(8 downto 0); -- tx_analogreset
tx_digitalreset : out std_logic_vector(8 downto 0); -- tx_digitalreset
tx_ready : out std_logic_vector(8 downto 0); -- tx_ready
pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
tx_cal_busy : in std_logic_vector(8 downto 0) := (others => 'X'); -- tx_cal_busy
rx_analogreset : out std_logic_vector(8 downto 0); -- rx_analogreset
rx_digitalreset : out std_logic_vector(8 downto 0); -- rx_digitalreset
rx_ready : out std_logic_vector(8 downto 0); -- rx_ready
rx_is_lockedtodata : in std_logic_vector(8 downto 0) := (others => 'X'); -- rx_is_lockedtodata
rx_cal_busy : in std_logic_vector(8 downto 0) := (others => 'X') -- rx_cal_busy
);
end component;
component ip_arria10_e2sg_transceiver_reset_controller_12
port (
clock : in std_logic := '0'; -- clock.clk
......
libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+ 56
− 46
View file @ 5e2a3e00
......@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#vlib ./work/ ;# Assume library work already exist
vmap altera_xcvr_native_a10_180 ./work/
vmap altera_common_sv_packages ./work/
......@@ -35,74 +35,84 @@ vmap altera_common_sv_packages ./work/
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_48
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_24
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_12
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_9
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_9/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_9_altera_xcvr_native_a10_180_gcmx4tq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_gcmx4tq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_6
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_6/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_6_altera_xcvr_native_a10_180_l3d7smq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_l3d7smq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_4
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_3
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# tse_sgmii_gx
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# jesd204b rx
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_180_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_180_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# jesd204b tx
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_xcvr_native_a10_180_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_xcvr_native_a10_180_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
+ 56
− 46
View file @ 5e2a3e00
......@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
#vlib ./work/ ;# Assume library work already exist
vmap altera_xcvr_native_a10_191 ./work/
vmap altera_common_sv_packages ./work/
......@@ -35,74 +35,84 @@ vmap altera_common_sv_packages ./work/
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_resync.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/alt_xcvr_arbiter.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_pcs.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_pma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_avmm.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/mentor/twentynm_xcvr_native.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/a10_avmm_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_pipe_retry.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_prbs_accum.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_odi_accel.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_arb.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_params_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_commands_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_functions_h.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_program.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_cpu.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/pcie_mgmt_master.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_pcie_dfe_ip.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_48
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_191_x2zy5gq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_x2zy5gq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_48_altera_xcvr_native_a10_191_x2zy5gq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_x2zy5gq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_24
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_12
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_9
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_9/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_9_altera_xcvr_native_a10_191_vl7iwaq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_vl7iwaq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_6
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_6/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_6_altera_xcvr_native_a10_191_evmmiyy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_evmmiyy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_4
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_3
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# tse_sgmii_gx
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_xcvr_native_a10_191_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_xcvr_native_a10_191_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# jesd204b rx
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_191_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_191_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# jesd204b tx
set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_xcvr_native_a10_191_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_xcvr_native_a10_191_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
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