Added missing r-6, r-9 items in tech_10gbase_r_component_pkg.vhd and ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl

Apply dp_ready FIFO flow control in generate loop, instead of using func_dp_stream_arr_set(dplink_siso_arr, dp_ready, 'READY')

Add debug signals. Correct single cycle rxlink_sysref. Correct FIFO data width to c_jesd204b_rx_framer_data_w.

RTSD-225: Renamed technology part agi027_xxxx into agi027_1e1v and Agi027_xxxx into Agi027_1e1v, the last four characters of the expected delivered type part, so 'xxxx = 1e1v'

RTSD-247: Created new Reset Release IPs version 1e1v for iwave using Agilex7 AGIB027R31B1E1V, that is necessary to use in all Stratix10 and Intel Agilex devices, for us in the iwave BSP (Boards). That was the result of a critical warning during synthesis.