splitted the terminationcontrol lines from the record types 't_tech_ddr_phy_in' and 't_tech_ddr_phy_ou'

Use g_rd_fifo_af_margin to fit one (DDR3 IP) or more (DDR4 IP) rd burst accesses of g_tech_ddr.maxburstsize each.

Added g_sim, when TRUE then use internal DDR memory model in tech_ddr component. When FALSE use DDR memory model in test bench.

Define t_mem_ctlr_mosi/miso in common_mem_pkg, to use that instead of the records defined in tech_ddr_pkg. Also remove t_tech_ddr_addr record because it is not needed.

Added io_ddr_cross_domain.vhd to handle dvr_clk and ctlr_clk domains in case they are different clock domains.

Redefined write flush modes. Now the flush is still under control by dvr_flush_en, and disabled when kept tied to '0'.

Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk available in same delta-cycle.

Ported $UNB ddr3.vhd to $RADIOHDL io_ddr.vhd. Initial version, still needs to be compiled and simulated with tb_io_ddr.vhd.