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Commit 3516f313 authored by Eric Kooistra's avatar Eric Kooistra
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Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk...

Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk available in same delta-cycle.
parent 0c866450
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...@@ -44,32 +44,43 @@ ENTITY io_ddr IS ...@@ -44,32 +44,43 @@ ENTITY io_ddr IS
g_flush_nof_channels : NATURAL := 0 g_flush_nof_channels : NATURAL := 0
); );
PORT ( PORT (
-- DDR reference clock
ctlr_ref_clk : IN STD_LOGIC; ctlr_ref_clk : IN STD_LOGIC;
ctlr_ref_rst : IN STD_LOGIC; ctlr_ref_rst : IN STD_LOGIC;
-- DDR controller clock domain
ctlr_clk_out : OUT STD_LOGIC;
ctlr_rst_out : OUT STD_LOGIC;
ctlr_clk_in : IN STD_LOGIC; -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
ctlr_rst_in : IN STD_LOGIC; -- connect ctlr_rst_out to ctlr_rst_in at top level
ctlr_init_done : OUT STD_LOGIC; ctlr_init_done : OUT STD_LOGIC;
ctlr_rdy : OUT STD_LOGIC; ctlr_rdy : OUT STD_LOGIC;
dvr_en : IN STD_LOGIC; dvr_en : IN STD_LOGIC;
dvr_wr_not_rd : IN STD_LOGIC; dvr_wr_not_rd : IN STD_LOGIC;
dvr_done : OUT STD_LOGIC;
dvr_start_addr : IN t_tech_ddr_addr; dvr_start_addr : IN t_tech_ddr_addr;
dvr_end_addr : IN t_tech_ddr_addr; dvr_end_addr : IN t_tech_ddr_addr;
dvr_done : OUT STD_LOGIC;
-- Write FIFO clock domain
wr_clk : IN STD_LOGIC; wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC; wr_rst : IN STD_LOGIC;
wr_sosi : IN t_dp_sosi; wr_sosi : IN t_dp_sosi;
wr_siso : OUT t_dp_siso; wr_siso : OUT t_dp_siso;
rd_sosi : OUT t_dp_sosi; -- Read FIFO clock domain
rd_siso : IN t_dp_siso;
rd_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC; rd_rst : IN STD_LOGIC;
rd_sosi : OUT t_dp_sosi;
rd_siso : IN t_dp_siso;
rd_fifo_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0); rd_fifo_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0);
-- DDR PHY external interface
phy_in : IN t_tech_ddr_phy_in; phy_in : IN t_tech_ddr_phy_in;
phy_io : INOUT t_tech_ddr_phy_io; phy_io : INOUT t_tech_ddr_phy_io;
phy_ou : OUT t_tech_ddr_phy_ou phy_ou : OUT t_tech_ddr_phy_ou
...@@ -91,9 +102,6 @@ ARCHITECTURE str OF io_ddr IS ...@@ -91,9 +102,6 @@ ARCHITECTURE str OF io_ddr IS
SIGNAL i_ctlr_init_done : STD_LOGIC; SIGNAL i_ctlr_init_done : STD_LOGIC;
SIGNAL i_dvr_done : STD_LOGIC; SIGNAL i_dvr_done : STD_LOGIC;
SIGNAL ctlr_gen_clk : STD_LOGIC;
SIGNAL ctlr_gen_rst : STD_LOGIC;
SIGNAL ctlr_mosi : t_tech_ddr_mosi := c_tech_ddr_mosi_rst; SIGNAL ctlr_mosi : t_tech_ddr_mosi := c_tech_ddr_mosi_rst;
SIGNAL ctlr_miso : t_tech_ddr_miso := c_tech_ddr_miso_rst; SIGNAL ctlr_miso : t_tech_ddr_miso := c_tech_ddr_miso_rst;
...@@ -128,8 +136,8 @@ BEGIN ...@@ -128,8 +136,8 @@ BEGIN
PORT MAP ( PORT MAP (
wr_rst => wr_rst, wr_rst => wr_rst,
wr_clk => wr_clk, wr_clk => wr_clk,
rd_rst => ctlr_gen_rst, rd_rst => ctlr_rst_in,
rd_clk => ctlr_gen_clk, rd_clk => ctlr_clk_in,
snk_out => wr_siso, snk_out => wr_siso,
snk_in => wr_sosi, snk_in => wr_sosi,
...@@ -149,8 +157,8 @@ BEGIN ...@@ -149,8 +157,8 @@ BEGIN
g_framed_xoff => FALSE -- immediately start flushing when dvr_flush goes high g_framed_xoff => FALSE -- immediately start flushing when dvr_flush goes high
) )
PORT MAP ( PORT MAP (
rst => ctlr_gen_rst, rst => ctlr_rst_in,
clk => ctlr_gen_clk, clk => ctlr_clk_in,
snk_in => flush_wr_sosi, snk_in => flush_wr_sosi,
snk_out => flush_wr_siso, snk_out => flush_wr_siso,
...@@ -193,8 +201,8 @@ BEGIN ...@@ -193,8 +201,8 @@ BEGIN
g_rd_fifo_rl => 1 g_rd_fifo_rl => 1
) )
PORT MAP ( PORT MAP (
wr_rst => ctlr_gen_rst, wr_rst => ctlr_rst_in,
wr_clk => ctlr_gen_clk, wr_clk => ctlr_clk_in,
rd_rst => rd_rst, rd_rst => rd_rst,
rd_clk => rd_clk, rd_clk => rd_clk,
...@@ -214,27 +222,25 @@ BEGIN ...@@ -214,27 +222,25 @@ BEGIN
g_tech_ddr => g_tech_ddr g_tech_ddr => g_tech_ddr
) )
PORT MAP ( PORT MAP (
rst => ctlr_gen_rst, rst => ctlr_rst_in,
clk => ctlr_gen_clk, clk => ctlr_clk_in,
ctlr_init_done => i_ctlr_init_done,
ctlr_mosi => ctlr_mosi,
ctlr_miso => ctlr_miso,
dvr_en => dvr_en, dvr_en => dvr_en,
dvr_done => i_dvr_done,
dvr_wr_not_rd => dvr_wr_not_rd, dvr_wr_not_rd => dvr_wr_not_rd,
dvr_start_addr => dvr_start_addr, dvr_start_addr => dvr_start_addr,
dvr_end_addr => dvr_end_addr, dvr_end_addr => dvr_end_addr,
dvr_done => i_dvr_done,
wr_fifo_usedw => wr_fifo_usedw, wr_fifo_usedw => wr_fifo_usedw,
wr_snk_out => ctlr_wr_snk_out,
wr_snk_in => ctlr_wr_snk_in, wr_snk_in => ctlr_wr_snk_in,
wr_snk_out => ctlr_wr_snk_out,
rd_src_out => ctlr_rd_src_out,
rd_src_in => ctlr_rd_src_in, rd_src_in => ctlr_rd_src_in,
rd_src_out => ctlr_rd_src_out
ctlr_init_done => i_ctlr_init_done,
ctlr_miso => ctlr_miso,
ctlr_mosi => ctlr_mosi
); );
u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
...@@ -248,8 +254,8 @@ BEGIN ...@@ -248,8 +254,8 @@ BEGIN
ctlr_ref_rst => ctlr_ref_rst, ctlr_ref_rst => ctlr_ref_rst,
-- Controller user interface -- Controller user interface
ctlr_gen_clk => ctlr_gen_clk, ctlr_gen_clk => ctlr_clk_out,
ctlr_gen_rst => ctlr_gen_rst, ctlr_gen_rst => ctlr_rst_out,
ctlr_gen_clk_2x => OPEN, ctlr_gen_clk_2x => OPEN,
ctlr_gen_rst_2x => OPEN, ctlr_gen_rst_2x => OPEN,
......
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
-- --
-- Testbench is selftesting: -- Testbench is selftesting:
-- --
-- > as 8
-- > run -all -- > run -all
-- --
...@@ -63,12 +64,15 @@ ARCHITECTURE str of tb_io_ddr IS ...@@ -63,12 +64,15 @@ ARCHITECTURE str of tb_io_ddr IS
TO_UVEC(2**c_tech_ddr_4g.a_col_w-1, c_tech_ddr_max.a_col_w)); TO_UVEC(2**c_tech_ddr_4g.a_col_w-1, c_tech_ddr_max.a_col_w));
CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr); CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctlr_data_w(c_tech_ddr);
CONSTANT c_dp_data_w : NATURAL := 32; --CONSTANT c_dp_data_w : NATURAL := 32;
CONSTANT c_dp_data_w : NATURAL := 256;
CONSTANT c_dp_factor : NATURAL := c_ctlr_data_w/c_dp_data_w; CONSTANT c_dp_factor : NATURAL := c_ctlr_data_w/c_dp_data_w;
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL ctlr_ref_clk : STD_LOGIC := '0'; SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_ref_rst : STD_LOGIC; SIGNAL ctlr_ref_rst : STD_LOGIC;
SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL ctlr_clk : STD_LOGIC;
SIGNAL ctlr_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC := '0'; SIGNAL dp_clk : STD_LOGIC := '0';
SIGNAL dp_rst : STD_LOGIC; SIGNAL dp_rst : STD_LOGIC;
...@@ -120,8 +124,8 @@ BEGIN ...@@ -120,8 +124,8 @@ BEGIN
dvr_wr_not_rd <= '0'; dvr_wr_not_rd <= '0';
snk_diag_en <= '0'; snk_diag_en <= '0';
proc_common_wait_until_high(dp_clk, ctlr_init_done); proc_common_wait_until_high(ctlr_clk, ctlr_init_done);
proc_common_wait_some_cycles(dp_clk, 2); -- Give the driver FSM a cycle to go into idle mode proc_common_wait_some_cycles(ctlr_clk, 2); -- Give the driver FSM a cycle to go into idle mode
-- START diagnostics source for write and sink for verify read -- START diagnostics source for write and sink for verify read
src_diag_en <= '1'; src_diag_en <= '1';
...@@ -130,25 +134,25 @@ BEGIN ...@@ -130,25 +134,25 @@ BEGIN
-- START WRITE -- START WRITE
dvr_wr_not_rd <= '1'; dvr_wr_not_rd <= '1';
dvr_en <= '1'; dvr_en <= '1';
proc_common_wait_some_cycles(dp_clk, 1); proc_common_wait_some_cycles(ctlr_clk, 1);
dvr_en <= '0'; dvr_en <= '0';
-- WRITE DONE -- WRITE DONE
proc_common_wait_some_cycles(dp_clk, 10); proc_common_wait_some_cycles(ctlr_clk, 10);
proc_common_wait_until_high(dp_clk, dvr_done); proc_common_wait_until_high(ctlr_clk, dvr_done);
-- START READ -- START READ
dvr_wr_not_rd <= '0'; dvr_wr_not_rd <= '0';
dvr_en <= '1'; dvr_en <= '1';
proc_common_wait_some_cycles(dp_clk, 1); proc_common_wait_some_cycles(ctlr_clk, 1);
dvr_en <= '0'; dvr_en <= '0';
-- READ DONE -- READ DONE
proc_common_wait_some_cycles(dp_clk, 10); proc_common_wait_some_cycles(ctlr_clk, 10);
proc_common_wait_until_high(dp_clk, dvr_done); proc_common_wait_until_high(ctlr_clk, dvr_done);
expected_cnt <= 1024*c_dp_factor; expected_cnt <= 1024*c_dp_factor;
proc_common_wait_some_cycles(dp_clk, 500*c_dp_factor); -- 'Done' means all requests are posted. Wait for the last read data to arrive. proc_common_wait_some_cycles(ctlr_clk, 500*c_dp_factor); -- 'Done' means all requests are posted. Wait for the last read data to arrive.
ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!" SEVERITY FAILURE; ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!" SEVERITY FAILURE;
ASSERT snk_diag_res = '0' REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE; ASSERT snk_diag_res = '0' REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;
...@@ -195,14 +199,20 @@ BEGIN ...@@ -195,14 +199,20 @@ BEGIN
ctlr_ref_clk => ctlr_ref_clk, ctlr_ref_clk => ctlr_ref_clk,
ctlr_ref_rst => ctlr_ref_rst, ctlr_ref_rst => ctlr_ref_rst,
ctlr_clk_out => ctlr_clk,
ctlr_rst_out => ctlr_rst,
ctlr_clk_in => ctlr_clk, -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
ctlr_rst_in => ctlr_rst,
ctlr_init_done => ctlr_init_done, ctlr_init_done => ctlr_init_done,
ctlr_rdy => ctlr_rdy, ctlr_rdy => ctlr_rdy,
dvr_start_addr => dvr_start_addr,
dvr_end_addr => dvr_end_addr,
dvr_en => dvr_en, dvr_en => dvr_en,
dvr_wr_not_rd => dvr_wr_not_rd, dvr_wr_not_rd => dvr_wr_not_rd,
dvr_done => dvr_done, dvr_done => dvr_done,
dvr_start_addr => dvr_start_addr,
dvr_end_addr => dvr_end_addr,
wr_clk => dp_clk, wr_clk => dp_clk,
wr_rst => dp_rst, wr_rst => dp_rst,
......
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