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RTSD
HDL
Commits
6bda9022
Commit
6bda9022
authored
10 years ago
by
Eric Kooistra
Browse files
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Use mosi/miso and sosi/siso records on the ports.
parent
c157ca31
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libraries/io/ddr/src/vhdl/io_ddr.vhd
+23
-35
23 additions, 35 deletions
libraries/io/ddr/src/vhdl/io_ddr.vhd
with
23 additions
and
35 deletions
libraries/io/ddr/src/vhdl/io_ddr.vhd
+
23
−
35
View file @
6bda9022
...
@@ -50,12 +50,11 @@ ENTITY io_ddr IS
...
@@ -50,12 +50,11 @@ ENTITY io_ddr IS
ctlr_init_done
:
OUT
STD_LOGIC
;
ctlr_init_done
:
OUT
STD_LOGIC
;
ctlr_rdy
:
OUT
STD_LOGIC
;
ctlr_rdy
:
OUT
STD_LOGIC
;
dvr_start_addr
:
IN
t_tech_ddr_addr
;
dvr_end_addr
:
IN
t_tech_ddr_addr
;
dvr_en
:
IN
STD_LOGIC
;
dvr_en
:
IN
STD_LOGIC
;
dvr_wr_not_rd
:
IN
STD_LOGIC
;
dvr_wr_not_rd
:
IN
STD_LOGIC
;
dvr_done
:
OUT
STD_LOGIC
;
dvr_done
:
OUT
STD_LOGIC
;
dvr_start_addr
:
IN
t_tech_ddr_addr
;
dvr_end_addr
:
IN
t_tech_ddr_addr
;
wr_clk
:
IN
STD_LOGIC
;
wr_clk
:
IN
STD_LOGIC
;
wr_rst
:
IN
STD_LOGIC
;
wr_rst
:
IN
STD_LOGIC
;
...
@@ -100,14 +99,14 @@ ARCHITECTURE str OF io_ddr IS
...
@@ -100,14 +99,14 @@ ARCHITECTURE str OF io_ddr IS
SIGNAL
dvr_flush
:
STD_LOGIC
:
=
'0'
;
SIGNAL
dvr_flush
:
STD_LOGIC
:
=
'0'
;
SIGNAL
ctlr_wr_s
iso
:
t_dp_siso
:
=
c_dp_siso_rdy
;
-- default xon='1'
SIGNAL
ctlr_wr_s
nk_out
:
t_dp_siso
:
=
c_dp_siso_rdy
;
-- default xon='1'
SIGNAL
ctlr_wr_s
osi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
ctlr_wr_s
nk_in
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
flush_wr_siso
:
t_dp_siso
;
SIGNAL
flush_wr_siso
:
t_dp_siso
;
SIGNAL
flush_wr_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
flush_wr_sosi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
ctlr_rd_s
iso
:
t_dp_siso
;
SIGNAL
ctlr_rd_s
rc_in
:
t_dp_siso
;
SIGNAL
ctlr_rd_s
osi
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
ctlr_rd_s
rc_out
:
t_dp_sosi
:
=
c_dp_sosi_rst
;
SIGNAL
wr_fifo_usedw
:
STD_LOGIC_VECTOR
(
ceil_log2
(
g_wr_fifo_depth
)
-1
DOWNTO
0
);
-- read side depth of the write FIFO
SIGNAL
wr_fifo_usedw
:
STD_LOGIC_VECTOR
(
ceil_log2
(
g_wr_fifo_depth
)
-1
DOWNTO
0
);
-- read side depth of the write FIFO
...
@@ -156,8 +155,8 @@ BEGIN
...
@@ -156,8 +155,8 @@ BEGIN
snk_in
=>
flush_wr_sosi
,
snk_in
=>
flush_wr_sosi
,
snk_out
=>
flush_wr_siso
,
snk_out
=>
flush_wr_siso
,
src_out
=>
ctlr_wr_s
osi
,
src_out
=>
ctlr_wr_s
nk_in
,
src_in
=>
ctlr_wr_s
iso
,
src_in
=>
ctlr_wr_s
nk_out
,
flush_en
=>
dvr_flush
flush_en
=>
dvr_flush
);
);
...
@@ -199,8 +198,8 @@ BEGIN
...
@@ -199,8 +198,8 @@ BEGIN
rd_rst
=>
rd_rst
,
rd_rst
=>
rd_rst
,
rd_clk
=>
rd_clk
,
rd_clk
=>
rd_clk
,
snk_out
=>
ctlr_rd_s
iso
,
snk_out
=>
ctlr_rd_s
rc_in
,
snk_in
=>
ctlr_rd_s
osi
,
snk_in
=>
ctlr_rd_s
rc_out
,
wr_usedw
=>
OPEN
,
wr_usedw
=>
OPEN
,
rd_usedw
=>
rd_fifo_usedw
,
rd_usedw
=>
rd_fifo_usedw
,
...
@@ -221,33 +220,22 @@ BEGIN
...
@@ -221,33 +220,22 @@ BEGIN
ctlr_init_done
=>
i_ctlr_init_done
,
ctlr_init_done
=>
i_ctlr_init_done
,
ctlr_rddata
=>
ctlr_miso
.
rddata
,
ctlr_mosi
=>
ctlr_mosi
,
ctlr_rdval
=>
ctlr_miso
.
rdval
,
ctlr_miso
=>
ctlr_miso
,
ctlr_waitrequest_n
=>
ctlr_miso
.
waitrequest_n
,
ctlr_address
=>
ctlr_mosi
.
address
,
ctlr_wrdata
=>
ctlr_mosi
.
wrdata
,
ctlr_wr_req
=>
ctlr_mosi
.
wr
,
ctlr_rd_req
=>
ctlr_mosi
.
rd
,
ctlr_burst
=>
ctlr_mosi
.
burstbegin
,
ctlr_burst_size
=>
ctlr_mosi
.
burstsize
,
wr_data
=>
ctlr_wr_sosi
.
data
,
wr_val
=>
ctlr_wr_sosi
.
valid
,
wr_ready
=>
ctlr_wr_siso
.
ready
,
rd_data
=>
ctlr_rd_sosi
.
data
,
rd_val
=>
ctlr_rd_sosi
.
valid
,
rd_ready
=>
ctlr_rd_siso
.
ready
,
start_addr
=>
dvr_start_addr
,
end_addr
=>
dvr_end_addr
,
dvr_en
=>
dvr_en
,
dvr_en
=>
dvr_en
,
dvr_wr_not_rd
=>
dvr_wr_not_rd
,
dvr_done
=>
i_dvr_done
,
dvr_done
=>
i_dvr_done
,
dvr_wr_not_rd
=>
dvr_wr_not_rd
,
dvr_start_addr
=>
dvr_start_addr
,
dvr_end_addr
=>
dvr_end_addr
,
wr_fifo_usedw
=>
wr_fifo_usedw
,
wr_snk_out
=>
ctlr_wr_snk_out
,
wr_snk_in
=>
ctlr_wr_snk_in
,
wr_fifo_usedw
=>
wr_fifo_usedw
rd_src_in
=>
ctlr_rd_src_in
,
rd_src_out
=>
ctlr_rd_src_out
);
);
u_tech_ddr
:
ENTITY
tech_ddr_lib
.
tech_ddr
u_tech_ddr
:
ENTITY
tech_ddr_lib
.
tech_ddr
...
...
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