Renamed wr_flush into wr_flush_en. Added purpose and description block diagram.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -20,6 +20,45 @@
 --
 --------------------------------------------------------------------------------
 
+-- Purpose: Provide streaming interface to DDR memory
+-- Description:
+--
+--   dvr_wr_fifo_usedw <----------------\
+--                                      |
+--            wr_sosi     wr_fifo_src   |   ctlr_wr_snk   ctlr_mosi
+--             .                .       |     .             .
+--             .     ________   .       |     .   _______   .   ______
+--             .    |        |--.-------+------->|       |  .  |      |
+--             .    |        |  .    ______   .  |       |  .  |      |
+--             .    |dp_fifo |  .   |      |  .  |       |  .  |      |
+--            ----->|dc_mixed|-+--->|dp    |---->|  io   |  .  | tech |
+--                  |widths  | |    |flush |     | ddr   |  .  | ddr  |
+--                  |________| |    |______|<-\  | driver|  .  |      |
+--                             |              |  |       |  .  |      |
+--                             |   wr_flush_en|  |       |  .  |      |
+--                             |     ______   |  |       |  .  |      |
+--                             \--->|io_ddr|--/  |       |  .  |      |
+--                                  |driver|     |       |  .  |      |
+--                             /--->|flush |     |       |  .  |      |
+--                             |/-->|ctrl  |<-\  |       |  .  |      |
+--                             ||/->|______|  |  |       |  .  |      |
+--                             |||            |  |       |  .  |      |<--- phy_in
+--   dvr_flush_en   -----------+||------------|->|       |---->|      |---> phy_out
+--   dvr_en         ------------+|------------|->|       |<----|      |<--> phy_io
+--   dvr_wr_not_rd  -------------+------------|->|       |  .  |      |
+--   dvr_done       <-------------------------+--|       |  .  |      |
+--   dvr_start_addr ---------------------------->|       |  .  |      |
+--   dvr_end_addr   ---------------------------->|       |  .  |      |
+--                   ________                    |       |  .  |      |
+--                  |dp_fifo |                   |       |  .  |      |
+--            <-----|dc_mixed|<------------------|       |  .  |      |
+--             .    |widths  |                .  |_______|  .  |______|
+--             .    |________|                .             .           
+--            rd_sosi                       ctlr_rd_src   ctlr_miso
+--            rd_fifo_usedw                               ctlr_init_done
+--         
+--
+
 LIBRARY IEEE, technology_lib, tech_ddr_lib, common_lib, dp_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
@@ -107,7 +146,7 @@ ARCHITECTURE str OF io_ddr IS
   SIGNAL ctlr_mosi         : t_tech_ddr_mosi := c_tech_ddr_mosi_rst;
   SIGNAL ctlr_miso         : t_tech_ddr_miso := c_tech_ddr_miso_rst;
 
-  SIGNAL wr_flush          : STD_LOGIC := '0';
+  SIGNAL wr_flush_en       : STD_LOGIC := '0';
  
   SIGNAL wr_fifo_snk_in    : t_dp_sosi;
   
@@ -170,8 +209,8 @@ BEGIN
   u_dp_flush : ENTITY dp_lib.dp_flush
   GENERIC MAP (
     g_ready_latency => 0,
-    g_framed_xon    => c_wr_fifo_use_ctrl,  -- stop flushing when wr_flush is low and a sop (or sync via sop) has arrived 
-    g_framed_xoff   => FALSE                -- immediately start flushing when wr_flush goes high
+    g_framed_xon    => c_wr_fifo_use_ctrl,  -- stop flushing when wr_flush_en is low and a sop (or sync via sop) has arrived 
+    g_framed_xoff   => FALSE                -- immediately start flushing when wr_flush_en goes high
   )
   PORT MAP (
     rst      => ctlr_rst_in,
@@ -183,7 +222,7 @@ BEGIN
     src_out  => ctlr_wr_snk_in,
     src_in   => ctlr_wr_snk_out,
 
-    flush_en => wr_flush
+    flush_en => wr_flush_en
   );
 
   p_wr_flush_snk_in : PROCESS (wr_fifo_src_out)
@@ -214,7 +253,7 @@ BEGIN
 
     wr_sosi       => wr_flush_snk_in,
 
-    wr_flush      => wr_flush
+    wr_flush_en   => wr_flush_en
   );
 
   u_rd_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
@@ -268,7 +307,7 @@ BEGIN
     ctlr_miso       => ctlr_miso,
     ctlr_mosi       => ctlr_mosi
   );
-
+  
   u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
   GENERIC MAP (
     g_technology => g_technology,
@@ -287,14 +326,14 @@ BEGIN
 
     ctlr_init_done    => i_ctlr_init_done,
 
-    ctrl_mosi         => ctlr_mosi,
-    ctrl_miso         => ctlr_miso,
+    ctlr_mosi         => ctlr_mosi,
+    ctlr_miso         => ctlr_miso,
 
     -- PHY interface
     phy_in            => phy_in,
     phy_io            => phy_io,
     phy_ou            => phy_ou
-  );
-
+  );             
+  
 END str;