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Commit e92d0677 authored by Eric Kooistra's avatar Eric Kooistra
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Use 'RANGE instead of g_wr_fifo_depth to know width of wr_fifo_usedw.

parent ab127a62
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......@@ -211,8 +211,7 @@ BEGIN
u_io_ddr_driver : ENTITY work.io_ddr_driver
GENERIC MAP (
g_tech_ddr => g_tech_ddr,
g_wr_fifo_depth => g_wr_fifo_depth
g_tech_ddr => g_tech_ddr
)
PORT MAP (
rst => ctlr_gen_rst,
......
......@@ -29,8 +29,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY io_ddr_driver IS
GENERIC (
g_tech_ddr : t_c_tech_ddr;
g_wr_fifo_depth : NATURAL := 128
g_tech_ddr : t_c_tech_ddr
);
PORT (
clk : IN STD_LOGIC;
......@@ -98,7 +97,7 @@ ARCHITECTURE str OF io_ddr_driver IS
SIGNAL addresses_rem : STD_LOGIC_VECTOR(31 DOWNTO 0); -- nof words (on the user side interface) to rd/wr until end addr is reached
SIGNAL reg_addresses_rem : STD_LOGIC_VECTOR(31 DOWNTO 0); -- nof words (on the user side interface) to rd/wr until end addr is reached
SIGNAL reg_wr_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth)-1 DOWNTO 0); -- read side depth of the write FIFO
SIGNAL reg_wr_fifo_usedw : STD_LOGIC_VECTOR(wr_fifo_usedw'RANGE); -- read side depth of the write FIFO
BEGIN
......
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