Prepare for DDR mosi/miso ports by adding ports ctlr_rddata,rdval and ctlr_address,wrdata.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -35,7 +35,7 @@ ENTITY io_ddr IS
     g_wr_data_w               : NATURAL := 32;  
     g_wr_use_ctrl             : BOOLEAN := FALSE;              -- TRUE to allow filling the WR FIFO (by disabling flush) after an EOP
     g_wr_fifo_depth           : NATURAL := 128;                -- >=16 AND >g_tech_ddr.maxburstsize                              , defined at read  side of write FIFO.
-    g_rd_fifo_depth           : NATURAL := 256;                -- >=16 AND >g_tech_ddr.maxburstsize > c_ddr_ctrl_nof_latent_reads, defined at write side of read  FIFO. 
+    g_rd_fifo_depth           : NATURAL := 256;                -- >=16 AND >g_tech_ddr.maxburstsize > c_ddr_ctlr_nof_latent_reads, defined at write side of read  FIFO. 
     g_rd_data_w               : NATURAL := 32;
     g_flush_wr_fifo           : BOOLEAN := FALSE;              -- TRUE instantiates a dp_flush + controller to flush the write fifo when the driver is not ready to write
     g_flush_sop               : BOOLEAN := FALSE;
@@ -69,7 +69,7 @@ ENTITY io_ddr IS
     rd_clk             : IN    STD_LOGIC;
     rd_rst             : IN    STD_LOGIC;
 
-    rd_fifo_usedw      : OUT   STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctrl_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0);
+    rd_fifo_usedw      : OUT   STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0);
     
     phy_in             : IN    t_tech_ddr_phy_in;
     phy_io             : INOUT t_tech_ddr_phy_io;
@@ -80,12 +80,11 @@ END io_ddr;
 
 ARCHITECTURE str OF io_ddr IS  
  
-  CONSTANT c_ctrl_address_w   : NATURAL := func_tech_ddr_ctrl_address_w(g_tech_ddr);
-  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctrl_data_w( g_tech_ddr);
+  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr);
   
   CONSTANT c_wr_fifo_depth    : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
 
-  CONSTANT c_ddr_ctrl_nof_latent_reads : NATURAL := 100;  -- Due to having a command cue, even after de-asserting read requests, the PHY keeps processing the cued read requests.
+  CONSTANT c_ddr_ctlr_nof_latent_reads : NATURAL := 100;  -- Due to having a command cue, even after de-asserting read requests, the PHY keeps processing the cued read requests.
                                                           -- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side.
                                                           
   CONSTANT c_latency       : NATURAL := 1;
@@ -99,7 +98,6 @@ ARCHITECTURE str OF io_ddr IS
   SIGNAL ctlr_mosi         : t_tech_ddr_mosi := c_tech_ddr_mosi_rst;
   SIGNAL ctlr_miso         : t_tech_ddr_miso := c_tech_ddr_miso_rst;
 
-  SIGNAL dvr_cur_addr      : t_tech_ddr_addr;
   SIGNAL dvr_flush         : STD_LOGIC := '0';
  
   SIGNAL ctlr_wr_siso      : t_dp_siso := c_dp_siso_rdy;  -- default xon='1'
@@ -192,7 +190,7 @@ BEGIN
     g_rd_data_w         => g_rd_data_w,
     g_use_ctrl          => FALSE,
     g_wr_fifo_size      => g_rd_fifo_depth,
-    g_wr_fifo_af_margin => c_ddr_ctrl_nof_latent_reads, -- >=4 (required by dp_fifo)
+    g_wr_fifo_af_margin => c_ddr_ctlr_nof_latent_reads, -- >=4 (required by dp_fifo)
     g_rd_fifo_rl        => 1
   )
   PORT MAP (
@@ -222,17 +220,26 @@ BEGIN
     clk             => ctlr_gen_clk,        
 
     ctlr_init_done  => i_ctlr_init_done,
-    ctlr_rdy        => ctlr_miso.waitrequest_n,
+    
+    ctlr_rddata     => ctlr_miso.rddata,
+    ctlr_rdval      => ctlr_miso.rdval,
+    ctlr_waitrequest_n => ctlr_miso.waitrequest_n,
+    
+    ctlr_address    => ctlr_mosi.address,
+    ctlr_wrdata     => ctlr_mosi.wrdata,
     ctlr_wr_req     => ctlr_mosi.wr,
     ctlr_rd_req     => ctlr_mosi.rd,
     ctlr_burst      => ctlr_mosi.burstbegin,
     ctlr_burst_size => ctlr_mosi.burstsize,
 
+    wr_data         => ctlr_wr_sosi.data,
     wr_val          => ctlr_wr_sosi.valid, 
-    wr_rdy          => ctlr_wr_siso.ready,
-    rd_rdy          => ctlr_rd_siso.ready,
+    wr_ready        => ctlr_wr_siso.ready,
+    
+    rd_data         => ctlr_rd_sosi.data,
+    rd_val          => ctlr_rd_sosi.valid,
+    rd_ready        => ctlr_rd_siso.ready,
 
-    cur_addr        => dvr_cur_addr,
     start_addr      => dvr_start_addr,
     end_addr        => dvr_end_addr, 
 
@@ -243,13 +250,6 @@ BEGIN
     wr_fifo_usedw   => wr_fifo_usedw
   );
 
-  ctlr_mosi.address(c_ctrl_address_w-1 DOWNTO 0) <= func_tech_ddr_ctrl_address(dvr_cur_addr, g_tech_ddr, c_ctrl_address_w);
-                                                    
-  ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0) <= ctlr_wr_sosi.data(c_ctlr_data_w-1 DOWNTO 0);
-    
-  ctlr_rd_sosi.valid                          <= ctlr_miso.rdval;
-  ctlr_rd_sosi.data(c_ctlr_data_w-1 DOWNTO 0) <= ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0);
-  
   u_tech_ddr : ENTITY tech_ddr_lib.tech_ddr
   GENERIC MAP (
     g_technology => g_technology,