Use func_tech_ddr_ctrl_address() for ctlr_mosi.address.

libraries/io/ddr/src/vhdl/io_ddr.vhd

@@ -81,7 +81,7 @@ END io_ddr;
 ARCHITECTURE str OF io_ddr IS  
  
   CONSTANT c_ctrl_address_w   : NATURAL := func_tech_ddr_ctrl_address_w(g_tech_ddr);
-  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctrl_data_w(   g_tech_ddr);
+  CONSTANT c_ctlr_data_w      : NATURAL := func_tech_ddr_ctrl_data_w( g_tech_ddr);
   
   CONSTANT c_wr_fifo_depth    : NATURAL := g_wr_fifo_depth * (c_ctlr_data_w/g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
 
@@ -96,20 +96,20 @@ ARCHITECTURE str OF io_ddr IS
   SIGNAL ctlr_gen_clk      : STD_LOGIC;
   SIGNAL ctlr_gen_rst      : STD_LOGIC;
   
-  SIGNAL ctlr_mosi         : t_tech_ddr_mosi;
-  SIGNAL ctlr_miso         : t_tech_ddr_miso;
+  SIGNAL ctlr_mosi         : t_tech_ddr_mosi := c_tech_ddr_mosi_rst;
+  SIGNAL ctlr_miso         : t_tech_ddr_miso := c_tech_ddr_miso_rst;
 
   SIGNAL dvr_cur_addr      : t_tech_ddr_addr;
   SIGNAL dvr_flush         : STD_LOGIC := '0';
  
   SIGNAL ctlr_wr_siso      : t_dp_siso := c_dp_siso_rdy;  -- default xon='1'
-  SIGNAL ctlr_wr_sosi      : t_dp_sosi;
+  SIGNAL ctlr_wr_sosi      : t_dp_sosi := c_dp_sosi_rst;
 
   SIGNAL flush_wr_siso     : t_dp_siso;
-  SIGNAL flush_wr_sosi     : t_dp_sosi;
+  SIGNAL flush_wr_sosi     : t_dp_sosi := c_dp_sosi_rst;
 
   SIGNAL ctlr_rd_siso      : t_dp_siso;
-  SIGNAL ctlr_rd_sosi      : t_dp_sosi;
+  SIGNAL ctlr_rd_sosi      : t_dp_sosi := c_dp_sosi_rst;
   
   SIGNAL wr_fifo_usedw     : STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth)-1 DOWNTO 0);  -- read side depth of the write FIFO
   
@@ -221,8 +221,8 @@ BEGIN
     rst             => ctlr_gen_rst,  
     clk             => ctlr_gen_clk,        
 
-    ctlr_rdy        => ctlr_miso.waitrequest_n,
     ctlr_init_done  => i_ctlr_init_done,
+    ctlr_rdy        => ctlr_miso.waitrequest_n,
     ctlr_wr_req     => ctlr_mosi.wr,
     ctlr_rd_req     => ctlr_mosi.rd,
     ctlr_burst      => ctlr_mosi.burstbegin,
@@ -243,10 +243,7 @@ BEGIN
     wr_fifo_usedw   => wr_fifo_usedw
   );
 
-  ctlr_mosi.address(c_ctrl_address_w-1 DOWNTO 0) <= dvr_cur_addr.chip &
-                                                    dvr_cur_addr.bank &
-                                                    dvr_cur_addr.row(g_tech_ddr.a_w-1 DOWNTO 0) &
-                                                    dvr_cur_addr.column(g_tech_ddr.a_col_w-1 DOWNTO g_tech_ddr.rsl_w);
+  ctlr_mosi.address(c_ctrl_address_w-1 DOWNTO 0) <= func_tech_ddr_ctrl_address(dvr_cur_addr, g_tech_ddr, c_ctrl_address_w);
                                                     
   ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0) <= ctlr_wr_sosi.data(c_ctlr_data_w-1 DOWNTO 0);