Use ctlr slv address instead of record address. Separate p_burst_size into wr and rd process and define burstsize as positive. Assign ctlr_mosi.burstsize directly using wr/rd_burst_size, no need for ctlr_mosi_burstsize.

Added io_ddr_cross_domain.vhd to handle dvr_clk and ctlr_clk domains in case they are different clock domains.

 . Quartus 14.1
 . Modelsim 10.4
 . Modelsim 6.6c path now includes '6.6c' as subdir.
-Note: dop233 has local mods that point to its own install dirs.

 waves and write them to HEX files used by the block gens;
-Added dp_stream_rec_play to apertif_unb1_correlator to record the WPFB output;
-Added tc_wpfb_src_out_arr.py to read and plot the recorded WPFB output;
 . Not working yet - the WPFB output does not resemble s spectrum.
-Commented out the correlator as the WPFB is now the main DUT.

Happy holidays!

-Added clock generation to mmm_apertif_unb1_correlator (for sim);
-Added werkplan.

Use same string lenght for all g_mode options, to avoid warning on always false in if statement when lengths do not match.

Redefined write flush modes. Now the flush is still under control by dvr_flush_en, and disabled when kept tied to '0'.

Clarified clock domains and use ctlr_clk_out and ctlr_clk_in to make ctlr_clk available in same delta-cycle.