Reordered ports.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -32,27 +32,25 @@ ENTITY io_ddr_driver IS
     g_tech_ddr         : t_c_tech_ddr
   );
   PORT ( 
-    clk                : IN  STD_LOGIC;
     rst                : IN  STD_LOGIC;
-
-    ctlr_init_done     : IN  STD_LOGIC;
-    
-    ctlr_mosi          : OUT t_tech_ddr_mosi;
-    ctlr_miso          : IN  t_tech_ddr_miso;
+    clk                : IN  STD_LOGIC;
 
     dvr_en             : IN  STD_LOGIC := '1';
     dvr_wr_not_rd      : IN  STD_LOGIC;       
-    dvr_done           : OUT STD_LOGIC; -- Requested wr or rd sequence is done.
     dvr_start_addr     : IN  t_tech_ddr_addr;
     dvr_end_addr       : IN  t_tech_ddr_addr;
+    dvr_done           : OUT STD_LOGIC;         -- Requested wr or rd sequence is done.
    
     wr_fifo_usedw      : IN  STD_LOGIC_VECTOR;
-    
-    wr_snk_out         : OUT t_dp_siso;
     wr_snk_in          : IN  t_dp_sosi;
+    wr_snk_out         : OUT t_dp_siso;
     
+    rd_src_out         : OUT t_dp_sosi;
     rd_src_in          : IN  t_dp_siso;
-    rd_src_out         : OUT t_dp_sosi
+    
+    ctlr_init_done     : IN  STD_LOGIC;
+    ctlr_miso          : IN  t_tech_ddr_miso;
+    ctlr_mosi          : OUT t_tech_ddr_mosi
    );
 END io_ddr_driver;
 
@@ -128,6 +126,12 @@ BEGIN
     END IF;
   END PROCESS;
 
+  -- Record address --> slv address
+  start_address <= func_tech_ddr_dq_address(dvr_start_addr, g_tech_ddr, c_address_w);
+  end_address   <= func_tech_ddr_dq_address(dvr_end_addr,   g_tech_ddr, c_address_w);
+  
+  cur_addr <= func_tech_ddr_dq_address(cur_address, g_tech_ddr);
+
   -- Add 1 address (accounting for address resulotion) to diff_address: we also want to write the last address. Shift the result right to provide the correct resolution.
   addresses_rem <= RESIZE_UVEC( SHIFT_UVEC( INCR_UVEC(diff_address, g_tech_ddr.rsl), g_tech_ddr.rsl_w), addresses_rem'LENGTH); 
   
@@ -165,7 +169,8 @@ BEGIN
   rd_src_out.valid <= ctlr_miso.rdval;
   rd_src_out.data <= RESIZE_DP_DATA(ctlr_miso.rddata);
   
-  p_state : PROCESS(prev_state, state, i_dvr_done, ctlr_miso, req_burst_cycles, dvr_wr_not_rd, wr_snk_in, wr_fifo_usedw, wr_burst_size, rd_burst_size, dvr_en, ctlr_init_done, reg_addresses_rem, rd_src_in, ctlr_mosi_burstsize, start_address, cur_address)
+  p_state : PROCESS(prev_state, state, ctlr_init_done, dvr_en, dvr_wr_not_rd, i_dvr_done, ctlr_mosi_burstsize, ctlr_miso, req_burst_cycles, wr_snk_in, rd_src_in, 
+                    wr_fifo_usedw, wr_burst_size, rd_burst_size, reg_addresses_rem, start_address, cur_address)
   BEGIN  
     nxt_state              <= state;   
     ctlr_mosi.wr           <= '0';
@@ -268,10 +273,5 @@ BEGIN
     END CASE;
   END PROCESS;
 
-  start_address <= func_tech_ddr_dq_address(dvr_start_addr, g_tech_ddr, c_address_w);
-  end_address   <= func_tech_ddr_dq_address(dvr_end_addr,   g_tech_ddr, c_address_w);
-  
-  cur_addr <= func_tech_ddr_dq_address(cur_address, g_tech_ddr);
-
 END str;