Use mosi/miso and sosi/siso records on the ports.

libraries/io/ddr/src/vhdl/io_ddr_driver.vhd

@@ -38,33 +38,22 @@ ENTITY io_ddr_driver IS
 
     ctlr_init_done     : IN  STD_LOGIC;
     
-    ctlr_rddata        : IN  STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
-    ctlr_rdval         : IN  STD_LOGIC;
-    ctlr_waitrequest_n : IN  STD_LOGIC;
+    ctlr_mosi          : OUT t_tech_ddr_mosi;
+    ctlr_miso          : IN  t_tech_ddr_miso;
     
-    ctlr_address       : OUT STD_LOGIC_VECTOR(c_tech_ddr_ctlr_address_w-1 DOWNTO 0);
-    ctlr_wrdata        : OUT STD_LOGIC_VECTOR(c_tech_ddr_ctlr_data_w-1 DOWNTO 0);
-    ctlr_burst         : OUT STD_LOGIC;
-    ctlr_burst_size    : OUT STD_LOGIC_VECTOR(c_tech_ddr_ctlr_burstsize_w-1 DOWNTO 0);
-    ctlr_wr_req        : OUT STD_LOGIC;   
-    ctlr_rd_req        : OUT STD_LOGIC;
-
     dvr_en             : IN  STD_LOGIC := '1';
     dvr_wr_not_rd      : IN  STD_LOGIC;       
     dvr_done           : OUT STD_LOGIC; -- Requested wr or rd sequence is done.
+    dvr_start_addr     : IN  t_tech_ddr_addr;
+    dvr_end_addr       : IN  t_tech_ddr_addr;
    
-    wr_data            : IN  STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0);
-    wr_val             : IN  STD_LOGIC; 
-    wr_ready           : OUT STD_LOGIC;
+    wr_fifo_usedw      : IN  STD_LOGIC_VECTOR;
     
-    rd_data            : OUT STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0);
-    rd_val             : OUT STD_LOGIC; 
-    rd_ready           : IN  STD_LOGIC;     
-
-    start_addr         : IN  t_tech_ddr_addr;
-    end_addr           : IN  t_tech_ddr_addr;
-
-    wr_fifo_usedw      : IN  STD_LOGIC_VECTOR
+    wr_snk_out         : OUT t_dp_siso;
+    wr_snk_in          : IN  t_dp_sosi;
+    
+    rd_src_in          : IN  t_dp_siso;
+    rd_src_out         : OUT t_dp_sosi
    );
 END io_ddr_driver;
 
@@ -93,7 +82,7 @@ ARCHITECTURE str OF io_ddr_driver IS
   SIGNAL nxt_wr_burst_size      : NATURAL;
   SIGNAL nxt_rd_burst_size      : NATURAL;
 
-  SIGNAL i_ctlr_burst_size      : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_burstsize_w-1 DOWNTO 0);
+  SIGNAL ctlr_mosi_burstsize    : STD_LOGIC_VECTOR(c_tech_ddr_ctlr_burstsize_w-1 DOWNTO 0);
 
   SIGNAL i_dvr_done             : STD_LOGIC;
   SIGNAL nxt_dvr_done           : STD_LOGIC;
@@ -113,7 +102,6 @@ ARCHITECTURE str OF io_ddr_driver IS
 
 BEGIN
 
-  ctlr_burst_size <= i_ctlr_burst_size;
   dvr_done        <= i_dvr_done; 
 
   p_clk : PROCESS(rst, clk)
@@ -171,31 +159,32 @@ BEGIN
     nxt_rd_burst_size <= v_burst_size;
   END PROCESS;
 
-  ctlr_address <= func_tech_ddr_ctlr_address(cur_addr, g_tech_ddr, c_tech_ddr_ctlr_address_w);
-  ctlr_wrdata <= RESIZE_DDR_CTLR_DATA(wr_data);
+  ctlr_mosi.address <= func_tech_ddr_ctlr_address(cur_addr, g_tech_ddr, c_tech_ddr_ctlr_address_w);
+  ctlr_mosi.wrdata <= RESIZE_DDR_CTLR_DATA(wr_snk_in.data);
+  ctlr_mosi.burstsize <= ctlr_mosi_burstsize;
 
-  rd_val  <= ctlr_rdval;
-  rd_data <= RESIZE_DP_DATA(ctlr_rddata);
+  rd_src_out.valid <= ctlr_miso.rdval;
+  rd_src_out.data <= RESIZE_DP_DATA(ctlr_miso.rddata);
   
-  p_state : PROCESS(prev_state, state, i_dvr_done, ctlr_waitrequest_n, req_burst_cycles, dvr_wr_not_rd, wr_val, wr_fifo_usedw, wr_burst_size, rd_burst_size, dvr_en, ctlr_init_done, reg_addresses_rem, rd_ready, i_ctlr_burst_size, start_address, cur_address)
+  p_state : PROCESS(prev_state, state, i_dvr_done, ctlr_miso, req_burst_cycles, dvr_wr_not_rd, wr_snk_in, wr_fifo_usedw, wr_burst_size, rd_burst_size, dvr_en, ctlr_init_done, reg_addresses_rem, rd_src_in, ctlr_mosi_burstsize, start_address, cur_address)
   BEGIN  
     nxt_state              <= state;   
-    ctlr_wr_req            <= '0';
-    ctlr_rd_req            <= '0';
-    ctlr_burst             <= '0'; 
-    i_ctlr_burst_size      <= (OTHERS => '0');
+    ctlr_mosi.wr           <= '0';
+    ctlr_mosi.rd           <= '0';
+    ctlr_mosi.burstbegin   <= '0'; 
+    ctlr_mosi_burstsize    <= (OTHERS => '0');
     nxt_req_burst_cycles   <= req_burst_cycles;
-    wr_ready               <= '0';
+    wr_snk_out.ready       <= '0';
     nxt_dvr_done           <= i_dvr_done;
     nxt_cur_address        <= cur_address;
 
     CASE state IS
      
       WHEN s_wr_burst => -- Performs the burst portion (word 2+)        
-        ctlr_wr_req <= '1';        
-        IF ctlr_waitrequest_n = '1' THEN -- when local_ready goes low, that cycle does not count as a burst cycle          
+        ctlr_mosi.wr <= '1';        
+        IF ctlr_miso.waitrequest_n = '1' THEN -- when local_ready goes low, that cycle does not count as a burst cycle          
           nxt_req_burst_cycles <= INCR_UVEC(req_burst_cycles, -1);
-          wr_ready             <= '1'; -- wr side uses latency of 0, so wr_ready<='1' acknowledges a successful write request.
+          wr_snk_out.ready     <= '1'; -- wr side uses latency of 0, so wr_snk_out.ready<='1' acknowledges a successful write request.
           IF UNSIGNED(req_burst_cycles) = 1 THEN -- Then we're in the last cycle of this burst sequence
             nxt_state <= s_wr_request; -- We can only initiate a burst through the wr_request state
           END IF;
@@ -206,21 +195,21 @@ BEGIN
         IF UNSIGNED(reg_addresses_rem) = 0 THEN -- end address reached
           nxt_dvr_done  <= '1';              
           nxt_state     <= s_idle;          
-        ELSIF ctlr_waitrequest_n = '1' THEN 
-          IF wr_val = '1' THEN
+        ELSIF ctlr_miso.waitrequest_n = '1' THEN 
+          IF wr_snk_in.valid = '1' THEN
             -- Always perform 1st write here             
-            ctlr_burst        <= '1'; -- assert burst begin: strictly this is a burst of 1. 
-            ctlr_wr_req       <= '1';            
-            wr_ready          <= '1';
-            i_ctlr_burst_size <= TO_DDR_CTLR_BURSTSIZE(1); -- Set ctlr_burst_size to 1 by default
+            wr_snk_out.ready     <= '1';
+            ctlr_mosi.wr         <= '1';
+            ctlr_mosi.burstbegin <= '1'; -- assert burst begin: strictly this is a burst of 1. 
+            ctlr_mosi_burstsize  <= TO_DDR_CTLR_BURSTSIZE(1); -- Set ctlr_mosi_burstsize to 1 by default
             IF wr_burst_size > 1 THEN
               -- Perform any remaining writes in a burst
               nxt_state            <= s_wr_burst;
               nxt_req_burst_cycles <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size-1); -- Forward the required nof burst cycles (-1 as we've done the 1st in this state already) to burst state
-              i_ctlr_burst_size    <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size  );
+              ctlr_mosi_burstsize  <= TO_DDR_CTLR_BURSTSIZE(wr_burst_size  );
             END IF; -- ELSE: there is only 1 word, so no need for remaining burst   
-            nxt_cur_address   <= INCR_UVEC(cur_address, UNSIGNED(i_ctlr_burst_size)*g_tech_ddr.rsl);
---            IF UNSIGNED(i_ctlr_burst_size) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
+            nxt_cur_address   <= INCR_UVEC(cur_address, UNSIGNED(ctlr_mosi_burstsize)*g_tech_ddr.rsl);
+--            IF UNSIGNED(ctlr_mosi_burstsize) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
 --            nxt_state <= s_wait3; 
 --            END IF;
           END IF;
@@ -232,14 +221,14 @@ BEGIN
           nxt_dvr_done  <= '1';              
           nxt_state     <= s_idle;
         ELSE 
-          IF rd_ready = '1' THEN -- Fifo uses its internal almost_full signal to toggle its snk_out.rdy     
-            IF ctlr_waitrequest_n = '1' THEN    
-              ctlr_rd_req       <= '1';                   
-              ctlr_burst        <= '1'; -- assert burst begin: strictly this is a burst of 1.                  
-              i_ctlr_burst_size <= TO_DDR_CTLR_BURSTSIZE(rd_burst_size);
-              IF rd_burst_size = 0 THEN i_ctlr_burst_size <= TO_DDR_CTLR_BURSTSIZE(1); END IF;
-              nxt_cur_address   <= INCR_UVEC(cur_address, UNSIGNED(i_ctlr_burst_size)*g_tech_ddr.rsl);  
---              IF UNSIGNED(i_ctlr_burst_size) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
+          IF rd_src_in.ready = '1' THEN -- Fifo uses its internal almost_full signal to toggle its snk_out.rdy     
+            IF ctlr_miso.waitrequest_n = '1' THEN    
+              ctlr_mosi.rd         <= '1';                   
+              ctlr_mosi.burstbegin <= '1'; -- assert burst begin: strictly this is a burst of 1.                  
+              ctlr_mosi_burstsize  <= TO_DDR_CTLR_BURSTSIZE(rd_burst_size);
+              IF rd_burst_size = 0 THEN ctlr_mosi_burstsize <= TO_DDR_CTLR_BURSTSIZE(1); END IF;
+              nxt_cur_address   <= INCR_UVEC(cur_address, UNSIGNED(ctlr_mosi_burstsize)*g_tech_ddr.rsl);  
+--              IF UNSIGNED(ctlr_mosi_burstsize) = 1 THEN -- Prevents FSM from going into this state again too soon (reg_addresses_rem invalid)
 --              nxt_state <= s_wait3; 
 --              END IF;
             END IF;           
@@ -280,8 +269,8 @@ BEGIN
     END CASE;
   END PROCESS;
 
-  end_address   <= func_tech_ddr_dq_address(  end_addr, g_tech_ddr, c_address_w);
-  start_address <= func_tech_ddr_dq_address(start_addr, g_tech_ddr, c_address_w);
+  start_address <= func_tech_ddr_dq_address(dvr_start_addr, g_tech_ddr, c_address_w);
+  end_address   <= func_tech_ddr_dq_address(dvr_end_addr,   g_tech_ddr, c_address_w);
   
   cur_addr <= func_tech_ddr_dq_address(cur_address, g_tech_ddr);