-Added IF statement to disable library subdir creation in case of 'unb2'.

tools/quartus/run_altera_simlib_comp

@@ -123,8 +123,10 @@ mv ../${FAMILY}_vhdl.log .
 #
 #    file.txt = the file name 
 
-sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_verilog.do
-sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_vhdl.do
+if [ "${TARGET}" = "unb2" ]; then
+  sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_verilog.do
+  sed -i 's/vlib/vlib -type directory/g' ${FAMILY}_vhdl.do
+fi
 
 # 4) Compile the Altera libraries with Modelsim
 $VSIM_DIR/vsim -c -do ${FAMILY}_verilog.do