Ported common FIFO IP from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk and verified it with tb_common_fifo_dc_mixed_widths.vhd.

Renamed memory_* into tech_memory_*, to more clearly show that the components are IP technology wrappers.

Need to declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.

Added read_modelsim_technology_libraries_file() to be able to add the technolgy libraries to the mpf.

Support local paths or using absolute paths with environment variables in the hdllib.cfg source files list.