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RTSD
HDL
Commits
97175962
Commit
97175962
authored
10 years ago
by
Eric Kooistra
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Corrected lib_names list in read_lib_compile_order_file(). Delete work lib before compile.
parent
5f3a4889
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tools/modelsim/commands.do
+8
-8
8 additions, 8 deletions
tools/modelsim/commands.do
with
8 additions
and
8 deletions
tools/modelsim/commands.do
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8
−
8
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97175962
...
@@ -192,15 +192,17 @@ proc mk_clean {arg_lib} {
...
@@ -192,15 +192,17 @@ proc mk_clean {arg_lib} {
}
}
proc
mk_compile
{
arg_lib
}
{
proc
mk_compile
{
arg_lib
}
{
set
sim
[
simdir
$arg_lib
]
if
{[
string
compare
[
env
]
"<No Context>"
]
!=
0
}
{
if
{[
string
compare
[
env
]
"<No Context>"
]
!=
0
}
{
puts
"A project cannot be closed while a simulation is in progress.\nUse the \"quit -sim\" command to unload the simulation first."
puts
"A project cannot be closed while a simulation is in progress.\nUse the \"quit -sim\" command to unload the simulation first."
return
return
}
}
puts
"\[mk compile $arg_lib\]"
puts
"\[mk compile $arg_lib\]"
lp
$arg_lib
lp
$arg_lib
if
{
!
[
file
exists
work
"
]}
then
{
if
{[
file
exists
"$sim/
work"
]}
then
{
v
lib
work
;
v
del
-
lib
$sim
/
work
-
all
}
}
vlib
work
project
compileall
project
compileall
}
}
...
@@ -217,16 +219,13 @@ proc mk_vmake {arg_lib} {
...
@@ -217,16 +219,13 @@ proc mk_vmake {arg_lib} {
mk_compile
$arg_lib
mk_compile
$arg_lib
}
}
puts
"\[mk vmake $arg_lib\]"
puts
"\[mk vmake $arg_lib\]"
if
{
!
[
file
exists
"$sim/makefile"
]
||
if
{
!
[
file
exists
"$sim/makefile"
]
||
([
file
mtime
"$sim/makefile"
]
<
[
file
mtime
"$sim/work/_info"
])
}
then
{
([
file
mtime
"$sim/makefile"
]
<
[
file
mtime
"$sim/work/_info"
])
}
then
{
# Both the specific library name $(arg_lib)_lib and the work library map to the same local work library,
# Both the specific library name $(arg_lib)_lib and the work library map to the same local work library,
# so to be compatible for both names always use work to generate the makefile
# so to be compatible for both names always use work to generate the makefile
puts
[
exec
vmake
-
fullsrcpath
work
>
$sim
/
makefile
]
puts
[
exec
vmake
-
fullsrcpath
work
>
$sim
/
makefile
]
}
}
if
{[
file
exists
"$sim/work"
]}
then
{
vdel
-
lib
$sim
/
work
-
all
vdel
-
lib
$sim
/
work
-
all
vlib
work
vlib
work
}
}
}
proc
mk_make
{
arg_lib
}
{
proc
mk_make
{
arg_lib
}
{
...
@@ -293,6 +292,7 @@ proc read_lib_compile_order_file {arg_lib} {
...
@@ -293,6 +292,7 @@ proc read_lib_compile_order_file {arg_lib} {
append
file_name
"_lib_order.txt"
append
file_name
"_lib_order.txt"
set
fp
[
open
$sim
/
$file_name
]
set
fp
[
open
$sim
/
$file_name
]
set
data
[
read
$fp
]
set
data
[
read
$fp
]
set
data
[
string
trim
$data
]
;
#
trim
any
trailing
white
space
close
$fp
close
$fp
set
lib_names
[
split
$data
]
set
lib_names
[
split
$data
]
puts
$lib_names
puts
$lib_names
...
...
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