Added technology DDIO files to RadioHDL.

libraries/technology/iobuf/hdllib.cfg

+hdl_lib_name = tech_iobuf
+hdl_library_clause_name = tech_iobuf_lib
+hdl_lib_uses = technology ip_altera_mf
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    tech_iobuf_component_pkg.vhd
+    tech_iobuf_ddio_in.vhd
+    tech_iobuf_ddio_out.vhd
+
+test_bench_files =

libraries/technology/iobuf/tech_iobuf_component_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: IP components declarations for various devices that get wrapped by the tech components
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+PACKAGE tech_iobuf_component_pkg IS
+
+  -----------------------------------------------------------------------------
+  -- altera_mf
+  -----------------------------------------------------------------------------
+  
+  COMPONENT altera_mf_ddio_in IS
+  GENERIC(
+    g_device_family : STRING := "Stratix IV";
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    in_dat      : IN  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_clk      : IN  STD_LOGIC;
+    in_clk_en   : IN  STD_LOGIC := '1';
+    rst         : IN  STD_LOGIC := '0';
+    out_dat_hi  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat_lo  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT altera_mf_ddio_out IS
+  GENERIC(
+    g_device_family : STRING  := "Stratix IV";
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    rst        : IN   STD_LOGIC := '0';
+    in_clk     : IN   STD_LOGIC;
+    in_clk_en  : IN   STD_LOGIC := '1';
+    in_dat_hi  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_dat_lo  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat    : OUT  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+END tech_iobuf_component_pkg;

libraries/technology/iobuf/tech_iobuf_ddio_in.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_iobuf_component_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_altera_mf_lib;
+
+ENTITY tech_iobuf_ddio_in IS
+  GENERIC (
+    g_technology    : NATURAL := c_tech_select_default;
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    in_dat      : IN  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_clk      : IN  STD_LOGIC;
+    in_clk_en   : IN  STD_LOGIC := '1';
+    rst         : IN  STD_LOGIC := '0';
+    out_dat_hi  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat_lo  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+END tech_iobuf_ddio_in;
+
+
+ARCHITECTURE str OF tech_iobuf_ddio_in IS
+
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_ddio_in
+    GENERIC MAP ("Stratix IV", g_width)
+    PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/iobuf/tech_iobuf_ddio_out.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_iobuf_component_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_altera_mf_lib;
+
+ENTITY tech_iobuf_ddio_out IS
+  GENERIC (
+    g_technology    : NATURAL := c_tech_select_default;
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    rst        : IN   STD_LOGIC := '0';
+    in_clk     : IN   STD_LOGIC;
+    in_clk_en  : IN   STD_LOGIC := '1';
+    in_dat_hi  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_dat_lo  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat    : OUT  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+END tech_iobuf_ddio_out;
+
+
+ARCHITECTURE str OF tech_iobuf_ddio_out IS
+
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_ddio_out
+    GENERIC MAP ("Stratix IV", g_width)
+    PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file