Added tech_fifo_* components.

libraries/technology/fifo/tech_fifo_component_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: IP components declarations for various devices that get wrapped by the tech components
+
+LIBRARY IEEE, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+PACKAGE tech_fifo_component_pkg IS
+
+  -----------------------------------------------------------------------------
+  -- altera_mf
+  -----------------------------------------------------------------------------
+  
+  COMPONENT altera_mf_fifo_sc IS
+  GENERIC (
+    g_use_eab    : STRING := "ON";
+    g_dat_w      : NATURAL;
+    g_nof_words  : NATURAL
+  );
+  PORT (
+    aclr  : IN STD_LOGIC;
+    clock : IN STD_LOGIC;
+    data  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdreq : IN STD_LOGIC;
+    wrreq : IN STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    full  : OUT STD_LOGIC;
+    q     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT altera_mf_fifo_dc IS
+  GENERIC (
+    g_dat_w      : NATURAL;
+    g_nof_words  : NATURAL
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC;
+    rdreq   : IN STD_LOGIC;
+    wrclk   : IN STD_LOGIC;
+    wrreq   : IN STD_LOGIC;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+  COMPONENT altera_mf_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_nof_words  : NATURAL;  -- FIFO size in nof wr_dat words
+    g_wrdat_w    : NATURAL;
+    g_rddat_w    : NATURAL
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC;
+    rdreq   : IN STD_LOGIC;
+    wrclk   : IN STD_LOGIC;
+    wrreq   : IN STD_LOGIC;
+    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+END tech_fifo_component_pkg;

libraries/technology/fifo/tech_fifo_dc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_fifo_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_altera_mf_lib;
+
+ENTITY tech_fifo_dc IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_dat_w      : NATURAL;
+    g_nof_words  : NATURAL
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC;
+    rdreq   : IN STD_LOGIC;
+    wrclk   : IN STD_LOGIC;
+    wrreq   : IN STD_LOGIC;
+    q       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END tech_fifo_dc;
+
+
+ARCHITECTURE str OF tech_fifo_dc IS
+
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_fifo_dc
+    GENERIC MAP (g_dat_w, g_nof_words)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_fifo_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_altera_mf_lib;
+
+ENTITY tech_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_nof_words  : NATURAL;  -- FIFO size in nof wr_dat words
+    g_wrdat_w    : NATURAL;
+    g_rddat_w    : NATURAL
+  );
+  PORT (
+    aclr    : IN STD_LOGIC  := '0';
+    data    : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+    rdclk   : IN STD_LOGIC;
+    rdreq   : IN STD_LOGIC;
+    wrclk   : IN STD_LOGIC;
+    wrreq   : IN STD_LOGIC;
+    q       : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+    rdempty : OUT STD_LOGIC;
+    rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+    wrfull  : OUT STD_LOGIC;
+    wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END tech_fifo_dc_mixed_widths;
+
+
+ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS
+
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_fifo_dc_mixed_widths
+    GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
+    PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/fifo/tech_fifo_sc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE work.tech_fifo_component_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_altera_mf_lib;
+
+ENTITY tech_fifo_sc IS
+  GENERIC (
+    g_technology : NATURAL := c_tech_select_default;
+    g_use_eab    : STRING := "ON";
+    g_dat_w      : NATURAL;
+    g_nof_words  : NATURAL
+  );
+  PORT (
+    aclr  : IN STD_LOGIC;
+    clock : IN STD_LOGIC;
+    data  : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    rdreq : IN STD_LOGIC;
+    wrreq : IN STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    full  : OUT STD_LOGIC;
+    q     : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+    usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END tech_fifo_sc;
+
+
+ARCHITECTURE str OF tech_fifo_sc IS
+
+BEGIN
+
+  gen_altera_mf : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : altera_mf_fifo_sc
+    GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
+    PORT MAP (aclr, clock, data, rdreq, wrreq, empty, full, q, usedw);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file