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Commit e6baeb74 authored by Eric Kooistra's avatar Eric Kooistra
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Ported common RAM, ROM components from... 

Ported common RAM, ROM components from /home/kooistra/svnroot/UniBoard_FP7/UniBoard/trunk to /home/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk.
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libraries/base/common/hdllib.cfg
+ 16
− 28
View file @ e6baeb74
hdl_lib_name = common
hdl_library_clause_name = common_lib
hdl_lib_uses = tst
hdl_lib_uses = technology technology_memory tst
build_sim_dir = $HDL_BUILD_DIR
build_synth_dir =
......@@ -16,11 +16,6 @@ synth_files =
$UNB/Firmware/modules/MegaWizard/fifo_sc/fifo_sc.vhd
$UNB/Firmware/modules/MegaWizard/fifo_dc/fifo_dc.vhd
$UNB/Firmware/modules/MegaWizard/fifo_dc/fifo_dc_mixed_widths.vhd
$UNB/Firmware/modules/MegaWizard/mem/rom_r.vhd
$UNB/Firmware/modules/MegaWizard/mem/ram_r_w.vhd
$UNB/Firmware/modules/MegaWizard/mem/ram_crw_crw.vhd
$UNB/Firmware/modules/MegaWizard/mem/ram_crwk_crw.vhd
$UNB/Firmware/modules/MegaWizard/mem/ram_cr_cw.vhd
$UNB/Firmware/modules/MegaWizard/arith/lut_add_sub.vhd
$UNB/Firmware/modules/MegaWizard/arith/dsp_add_sub.vhd
$UNB/Firmware/modules/MegaWizard/arith/dsp_mult_add2.vhd
......@@ -29,6 +24,21 @@ synth_files =
$UNB/Firmware/modules/common/src/ip/MegaWizard/iobuf_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_sl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_integer.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_natural.vhd
src/vhdl/common_ram_crw_crw_ratio.vhd
src/vhdl/common_ram_cr_cw_ratio.vhd
src/vhdl/common_ram_crw_crw.vhd
src/vhdl/common_ram_crw_cr.vhd
src/vhdl/common_ram_crw_cw.vhd
src/vhdl/common_ram_cr_cw.vhd
src/vhdl/common_ram_rw_rw.vhd
src/vhdl/common_ram_r_w.vhd
src/vhdl/common_rom.vhd
$UNB/Firmware/modules/common/src/vhdl/common_wideband_data_scope.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in.vhd
$UNB/Firmware/modules/common/src/vhdl/common_iobuf_in_a_stratix4.vhd
......@@ -42,10 +52,6 @@ synth_files =
$UNB/Firmware/modules/common/src/vhdl/common_areset.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture.vhd
$UNB/Firmware/modules/common/src/vhdl/common_acapture_slv.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_sl.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_integer.vhd
$UNB/Firmware/modules/common/src/vhdl/common_pipeline_natural.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout.vhd
$UNB/Firmware/modules/common/src/vhdl/common_fanout_tree.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ddreg.vhd
......@@ -127,27 +133,9 @@ synth_files =
$UNB/Firmware/modules/common/src/vhdl/common_reg_cross_domain.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reg_r_w.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reg_r_w_dc.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_crw_ratio.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_crw_ratio_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_crw.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_crw_a_stratix4.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_cr.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_cr_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_cw.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_crw_cw_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_cr_cw.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_cr_cw_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_cr_cw_ratio.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_cr_cw_ratio_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_rw_rw.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_rw_rw_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_r_w.vhd
$UNB/Firmware/modules/common/src/vhdl/common_interleave.vhd
$UNB/Firmware/modules/common/src/vhdl/common_deinterleave.vhd
$UNB/Firmware/modules/common/src/vhdl/common_reinterleave.vhd
$UNB/Firmware/modules/common/src/vhdl/common_ram_r_w_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_rom.vhd
$UNB/Firmware/modules/common/src/vhdl/common_rom_a_str.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_reg.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_ram_crw_crw.vhd
$UNB/Firmware/modules/common/src/vhdl/common_paged_ram_rw_rw.vhd
......
libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+ 8
− 5
View file @ e6baeb74
......@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_cr_cw IS
GENERIC (
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
);
PORT (
-- Write port clock domain
......@@ -58,8 +60,9 @@ BEGIN
u_cr_cw : ENTITY work.common_ram_crw_crw
GENERIC MAP (
g_ram => g_ram,
g_init_file => g_init_file
g_technology => g_technology,
g_ram => g_ram,
g_init_file => g_init_file
)
PORT MAP (
rst_a => wr_rst,
......
libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+ 10
− 7
View file @ e6baeb74
......@@ -19,15 +19,17 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_cr_cw_ratio IS
GENERIC (
g_ram_wr : t_c_mem := c_mem_ram; -- settings for port a
g_ram_rd : t_c_mem := c_mem_ram; -- data width and address range for port b
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram_wr : t_c_mem := c_mem_ram; -- settings for port a
g_ram_rd : t_c_mem := c_mem_ram; -- data width and address range for port b
g_init_file : STRING := "UNUSED"
);
PORT (
-- Write port clock domain
......@@ -59,9 +61,10 @@ BEGIN
u_cr_cw : ENTITY work.common_ram_crw_crw_ratio
GENERIC MAP (
g_ram_a => g_ram_wr,
g_ram_b => g_ram_rd,
g_init_file => g_init_file
g_technology => g_technology,
g_ram_a => g_ram_wr,
g_ram_b => g_ram_rd,
g_init_file => g_init_file
)
PORT MAP (
rst_a => wr_rst,
......
libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+ 8
− 5
View file @ e6baeb74
......@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_crw_cr IS
GENERIC (
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
);
PORT (
-- MM read/write port clock domain
......@@ -62,8 +64,9 @@ BEGIN
u_crw_cr : ENTITY work.common_ram_crw_crw
GENERIC MAP (
g_ram => g_ram,
g_init_file => g_init_file
g_technology => g_technology,
g_ram => g_ram,
g_init_file => g_init_file
)
PORT MAP (
rst_a => mm_rst,
......
libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+ 140
− 2
View file @ e6baeb74
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
......@@ -19,12 +19,15 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib, technology_memory_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_pkg.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_crw_crw IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED";
g_true_dual_port : BOOLEAN := TRUE
......@@ -50,3 +53,138 @@ ENTITY common_ram_crw_crw IS
rd_val_b : OUT STD_LOGIC
);
END common_ram_crw_crw;
ARCHITECTURE str OF common_ram_crw_crw IS
CONSTANT c_rd_latency : NATURAL := sel_a_b(g_ram.latency<2, g_ram.latency, 2); -- handle read latency 1 or 2 in RAM
CONSTANT c_pipeline : NATURAL := sel_a_b(g_ram.latency>c_rd_latency, g_ram.latency-c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
-- Intermediate signal for extra pipelining
SIGNAL ram_rd_dat_a : STD_LOGIC_VECTOR(rd_dat_a'RANGE);
SIGNAL ram_rd_dat_b : STD_LOGIC_VECTOR(rd_dat_b'RANGE);
-- Map sl to single bit slv for rd_val pipelining
SIGNAL ram_rd_en_a : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL ram_rd_en_b : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL ram_rd_val_a : STD_LOGIC_VECTOR(0 DOWNTO 0);
SIGNAL ram_rd_val_b : STD_LOGIC_VECTOR(0 DOWNTO 0);
BEGIN
ASSERT g_ram.latency >= 1
REPORT "common_ram_crw_crw : only support read latency >= 1"
SEVERITY FAILURE;
-- memory access
gen_true_dual_port : IF g_true_dual_port = TRUE GENERATE
u_ram : ENTITY technology_memory_lib.memory_ram_crw_crw
GENERIC MAP (
g_technology => g_technology,
g_adr_w => g_ram.adr_w,
g_dat_w => g_ram.dat_w,
g_nof_words => g_ram.nof_dat,
g_rd_latency => c_rd_latency,
g_init_file => g_init_file
)
PORT MAP (
clock_a => clk_a,
clock_b => clk_b,
enable_a => clken_a,
enable_b => clken_b,
wren_a => wr_en_a,
wren_b => wr_en_b,
data_a => wr_dat_a,
data_b => wr_dat_b,
address_a => adr_a,
address_b => adr_b,
q_a => ram_rd_dat_a,
q_b => ram_rd_dat_b
);
END GENERATE;
gen_simple_dual_port : IF g_true_dual_port = FALSE GENERATE
u_ram : ENTITY technology_memory_lib.memory_ram_cr_cw
GENERIC MAP (
g_technology => g_technology,
g_adr_w => g_ram.adr_w,
g_dat_w => g_ram.dat_w,
g_nof_words => g_ram.nof_dat,
g_rd_latency => c_rd_latency,
g_init_file => g_init_file
)
PORT MAP
(
wrclock => clk_a,
wrclocken => clken_a,
wren => wr_en_a,
wraddress => adr_a,
data => wr_dat_a,
rdclock => clk_b,
rdclocken => clken_b,
rdaddress => adr_b,
q => ram_rd_dat_b
);
END GENERATE;
-- read output
u_pipe_a : ENTITY work.common_pipeline
GENERIC MAP (
g_pipeline => c_pipeline,
g_in_dat_w => g_ram.dat_w,
g_out_dat_w => g_ram.dat_w
)
PORT MAP (
clk => clk_a,
clken => clken_a,
in_dat => ram_rd_dat_a,
out_dat => rd_dat_a
);
u_pipe_b : ENTITY work.common_pipeline
GENERIC MAP (
g_pipeline => c_pipeline,
g_in_dat_w => g_ram.dat_w,
g_out_dat_w => g_ram.dat_w
)
PORT MAP (
clk => clk_b,
clken => clken_b,
in_dat => ram_rd_dat_b,
out_dat => rd_dat_b
);
-- rd_val control
ram_rd_en_a(0) <= rd_en_a;
ram_rd_en_b(0) <= rd_en_b;
rd_val_a <= ram_rd_val_a(0);
rd_val_b <= ram_rd_val_b(0);
u_rd_val_a : ENTITY work.common_pipeline
GENERIC MAP (
g_pipeline => g_ram.latency,
g_in_dat_w => 1,
g_out_dat_w => 1
)
PORT MAP (
clk => clk_a,
clken => clken_a,
in_dat => ram_rd_en_a,
out_dat => ram_rd_val_a
);
u_rd_val_b : ENTITY work.common_pipeline
GENERIC MAP (
g_pipeline => g_ram.latency,
g_in_dat_w => 1,
g_out_dat_w => 1
)
PORT MAP (
clk => clk_b,
clken => clken_b,
in_dat => ram_rd_en_b,
out_dat => ram_rd_val_b
);
END str;
libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+ 8
− 5
View file @ e6baeb74
......@@ -19,16 +19,18 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib, technology_memory_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_pkg.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_crw_crw_ratio IS
GENERIC (
g_ram_a : t_c_mem := c_mem_ram; -- settings for port a
g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram_a : t_c_mem := c_mem_ram; -- settings for port a
g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b
g_init_file : STRING := "UNUSED"
);
PORT (
rst_a : IN STD_LOGIC := '0';
......@@ -81,8 +83,9 @@ BEGIN
SEVERITY FAILURE;
-- memory access
u_ramk : ENTITY work.ram_crwk_crw
u_ramk : ENTITY technology_memory_lib.memory_ram_crwk_crw
GENERIC MAP (
g_technology => g_technology,
g_adr_a_w => g_ram_a.adr_w,
g_adr_b_w => g_ram_b.adr_w,
g_dat_a_w => g_ram_a.dat_w,
......
libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+ 8
− 5
View file @ e6baeb74
......@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_crw_cw IS
GENERIC (
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
);
PORT (
-- MM read/write port clock domain
......@@ -61,8 +63,9 @@ BEGIN
u_crw_cw : ENTITY work.common_ram_crw_crw
GENERIC MAP (
g_ram => g_ram,
g_init_file => g_init_file
g_technology => g_technology,
g_ram => g_ram,
g_init_file => g_init_file
)
PORT MAP (
rst_a => mm_rst,
......
libraries/base/common/src/vhdl/common_ram_r_w.vhd
+ 8
− 5
View file @ e6baeb74
......@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_r_w IS
GENERIC (
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
);
PORT (
rst : IN STD_LOGIC := '0';
......@@ -52,8 +54,9 @@ BEGIN
u_rw_rw : ENTITY work.common_ram_rw_rw
GENERIC MAP (
g_ram => g_ram,
g_init_file => g_init_file
g_technology => g_technology,
g_ram => g_ram,
g_init_file => g_init_file
)
PORT MAP (
rst => rst,
......
libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+ 8
− 5
View file @ e6baeb74
......@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_ram_rw_rw IS
GENERIC (
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
);
PORT (
rst : IN STD_LOGIC := '0';
......@@ -56,8 +58,9 @@ BEGIN
u_crw_crw : ENTITY work.common_ram_crw_crw
GENERIC MAP (
g_ram => g_ram,
g_init_file => g_init_file
g_technology => g_technology,
g_ram => g_ram,
g_init_file => g_init_file
)
PORT MAP (
rst_a => rst,
......
libraries/base/common/src/vhdl/common_rom.vhd
+ 8
− 5
View file @ e6baeb74
......@@ -19,14 +19,16 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE work.common_mem_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY common_rom IS
GENERIC (
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
g_technology : NATURAL := c_tech_select_default;
g_ram : t_c_mem := c_mem_ram;
g_init_file : STRING := "UNUSED"
);
PORT (
rst : IN STD_LOGIC := '0';
......@@ -48,8 +50,9 @@ BEGIN
u_r_w : ENTITY work.common_ram_r_w
GENERIC MAP (
g_ram => g_ram,
g_init_file => g_init_file
g_technology => g_technology,
g_ram => g_ram,
g_init_file => g_init_file
)
PORT MAP (
rst => rst,
......
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