Moved or copied files from UniBoard to RadioHDL.

libraries/base/common/src/vhdl/common_ram_crw_crw.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE work.common_mem_pkg.ALL;
+
+ENTITY common_ram_crw_crw IS
+  GENERIC (
+    g_ram            : t_c_mem := c_mem_ram;
+    g_init_file      : STRING  := "UNUSED";
+    g_true_dual_port : BOOLEAN := TRUE
+  );
+  PORT (
+    rst_a     : IN  STD_LOGIC := '0';
+    rst_b     : IN  STD_LOGIC := '0';
+    clk_a     : IN  STD_LOGIC;
+    clk_b     : IN  STD_LOGIC;
+    clken_a   : IN  STD_LOGIC := '1';
+    clken_b   : IN  STD_LOGIC := '1';
+    wr_en_a   : IN  STD_LOGIC := '0';
+    wr_en_b   : IN  STD_LOGIC := '0';
+    wr_dat_a  : IN  STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+    wr_dat_b  : IN  STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+    adr_a     : IN  STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+    adr_b     : IN  STD_LOGIC_VECTOR(g_ram.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+    rd_en_a   : IN  STD_LOGIC := '1';
+    rd_en_b   : IN  STD_LOGIC := '1';
+    rd_dat_a  : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0);
+    rd_dat_b  : OUT STD_LOGIC_VECTOR(g_ram.dat_w-1 DOWNTO 0);
+    rd_val_a  : OUT STD_LOGIC;
+    rd_val_b  : OUT STD_LOGIC
+  );
+END common_ram_crw_crw;