Moved or copied FIFO files from UniBoard to RadioHDL.

libraries/base/common/src/vhdl/common_fifo_dc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Dual clock FIFO
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY common_fifo_dc IS
+  GENERIC (
+    g_note_is_ful : BOOLEAN := TRUE;   -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+    g_fail_rd_emp : BOOLEAN := FALSE;  -- when TRUE report FAILURE when read from an empty FIFO
+    g_dat_w       : NATURAL := 36;
+    g_nof_words   : NATURAL := 256   -- 36 * 256 = 1 M9K
+  );
+  PORT (
+    rst     : IN  STD_LOGIC;
+    wr_clk  : IN  STD_LOGIC;
+    wr_dat  : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    wr_req  : IN  STD_LOGIC;
+    wr_ful  : OUT STD_LOGIC;
+    wrusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
+    rd_clk  : IN  STD_LOGIC;
+    rd_dat  : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    rd_req  : IN  STD_LOGIC;
+    rd_emp  : OUT STD_LOGIC;
+    rdusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
+    rd_val  : OUT STD_LOGIC := '0'    
+  );
+END common_fifo_dc;
+

libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Dual clock - dual width FIFO to exchange clock rate and data width
+-- Description:
+-- . For g_wr_dat_w=8 and g_rd_dat_w=16 the read result data for writing
+--   counter data is: 
+--     wr_dat:  00, 01, 02, 03, ...
+--     rd_dat:          0100,  0302, ...
+--   Hence there is only read data available when the whole rd_dat word has
+--   been filled by the wr_dat words. Also the read empty remains active until
+--   the whole rd_dat word has been filled.
+-- . For g_wr_dat_w=8 and g_rd_dat_w=4 the read result data for writing
+--   counter data is: 
+--     wr_dat:  00,    01,    02,    03, ...
+--     rd_dat:     0,0,   1,0,   2,0,   3,0, ...
+-- Remark:
+-- . The MegaWizard dual width FIFO is only available as dual clock FIFO.
+--
+-- Warning !!!
+-- . It appears that the stratix4 architecture does not work OK when g_rd_dat_w
+--   is not a power of 2 multiple of g_wr_dat_w. After that g_nof_words have
+--   been written to the FIFO the rdusedw will wrap and the output goes wrong.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY common_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_note_is_ful : BOOLEAN := TRUE;   -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+    g_fail_rd_emp : BOOLEAN := FALSE;  -- when TRUE report FAILURE when read from an empty FIFO
+    g_nof_words   : NATURAL := c_bram_m9k_fifo_depth;  -- FIFO size in nof wr_dat words
+    g_wr_dat_w    : NATURAL := 36;   -- 36 * 256 = 1 M9K
+    g_rd_dat_w    : NATURAL := 9
+  );
+  PORT (
+    rst     : IN  STD_LOGIC;
+    wr_clk  : IN  STD_LOGIC;
+    wr_dat  : IN  STD_LOGIC_VECTOR(g_wr_dat_w-1 DOWNTO 0);
+    wr_req  : IN  STD_LOGIC;
+    wr_ful  : OUT STD_LOGIC;
+    wrusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0);
+    rd_clk  : IN  STD_LOGIC;
+    rd_dat  : OUT STD_LOGIC_VECTOR(g_rd_dat_w-1 DOWNTO 0);
+    rd_req  : IN  STD_LOGIC;
+    rd_emp  : OUT STD_LOGIC;
+    rdusedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words*g_wr_dat_w/g_rd_dat_w)-1 DOWNTO 0);
+    rd_val  : OUT STD_LOGIC    
+  );
+END common_fifo_dc_mixed_widths;
+

libraries/base/common/src/vhdl/common_fifo_sc.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Single clock FIFO
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+ENTITY common_fifo_sc IS
+  GENERIC (
+    g_note_is_ful : BOOLEAN := TRUE;   -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
+    g_fail_rd_emp : BOOLEAN := FALSE;  -- when TRUE report FAILURE when read from an empty FIFO
+    g_use_lut     : BOOLEAN := FALSE;  -- when TRUE then force using LUTs via Altera eab="OFF",
+                                       -- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
+                                       --      there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
+    g_reset       : BOOLEAN := FALSE;  -- when TRUE release FIFO reset some cycles after rst release, else use rst directly
+    g_init        : BOOLEAN := FALSE;  -- when TRUE force wr_req inactive for some cycles after FIFO reset release, else use wr_req as is
+    g_dat_w       : NATURAL := 36;     -- 36 * 256 = 1 M9K
+    g_nof_words   : NATURAL := c_bram_m9k_fifo_depth;
+    g_af_margin   : NATURAL := 0       -- FIFO almost full margin for wr_aful flagging
+  );
+  PORT (
+    rst      : IN  STD_LOGIC;
+    clk      : IN  STD_LOGIC;
+    wr_dat   : IN  STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    wr_req   : IN  STD_LOGIC;
+    wr_ful   : OUT STD_LOGIC;
+    wr_aful  : OUT STD_LOGIC;          -- registered FIFO almost full flag
+    rd_dat   : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+    rd_req   : IN  STD_LOGIC;
+    rd_emp   : OUT STD_LOGIC;
+    rd_val   : OUT STD_LOGIC;
+    usedw    : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0)
+  );
+END common_fifo_sc;
+

libraries/technology/altera/altera_mf/altera_mf_fifo_dc.vhd

+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo 
+
+-- ============================================================
+-- File Name: altera_mf_fifo_dc.vhd
+-- Megafunction Name(s):
+-- 			dcfifo
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY common_lib;
+USE common_lib.common_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altera_mf_fifo_dc IS
+  GENERIC (
+    g_dat_w     : NATURAL;
+    g_nof_words : NATURAL
+  );
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		rdusedw		: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+		wrfull		: OUT STD_LOGIC ;
+		wrusedw		: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+	);
+END altera_mf_fifo_dc;
+
+
+ARCHITECTURE SYN OF altera_mf_fifo_dc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdempty	: OUT STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			wrfull	: OUT STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+			rdusedw	: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	rdempty    <= sub_wire0;
+	wrusedw    <= sub_wire1(ceil_log2(g_nof_words)-1 DOWNTO 0);
+	wrfull    <= sub_wire2;
+	q    <= sub_wire3(g_dat_w-1 DOWNTO 0);
+	rdusedw    <= sub_wire4(ceil_log2(g_nof_words)-1 DOWNTO 0);
+
+	dcfifo_component : dcfifo
+	GENERIC MAP (
+		intended_device_family => "Stratix IV",
+		lpm_numwords => g_nof_words,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => g_dat_w,
+		lpm_widthu => ceil_log2(g_nof_words),
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "ON",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		rdempty => sub_wire0,
+		wrusedw => sub_wire1,
+		wrfull => sub_wire2,
+		q => sub_wire3,
+		rdusedw => sub_wire4
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+-- Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

libraries/technology/altera/altera_mf/altera_mf_fifo_dc_mixed_widths.vhd

+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: altera_mf_fifo_dc_mixed_widths.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.0 Build 218 06/27/2010 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY common_lib;
+USE common_lib.common_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altera_mf_fifo_dc_mixed_widths IS
+  GENERIC (
+    g_nof_words : NATURAL;  -- FIFO size in nof wr_dat words
+    g_wrdat_w   : NATURAL;
+    g_rddat_w   : NATURAL
+  );
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		rdusedw		: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+		wrfull		: OUT STD_LOGIC ;
+		wrusedw		: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+	);
+END altera_mf_fifo_dc_mixed_widths;
+
+
+ARCHITECTURE SYN OF altera_mf_fifo_dc_mixed_widths IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (q'RANGE);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (wrusedw'RANGE);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (rdusedw'RANGE);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			rdclk	: IN STD_LOGIC ;
+			wrfull	: OUT STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (q'RANGE);
+			rdempty	: OUT STD_LOGIC ;
+			wrclk	: IN STD_LOGIC ;
+			wrreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (wrusedw'RANGE);
+			aclr	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (data'RANGE);
+			rdreq	: IN STD_LOGIC ;
+			rdusedw	: OUT STD_LOGIC_VECTOR (rdusedw'RANGE)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrfull    <= sub_wire0;
+	q    <= sub_wire1(q'RANGE);
+	rdempty    <= sub_wire2;
+	wrusedw    <= sub_wire3(wrusedw'RANGE);
+	rdusedw    <= sub_wire4(rdusedw'RANGE);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Stratix IV",
+		lpm_numwords => g_nof_words,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => g_wrdat_w,
+		lpm_widthu => ceil_log2(g_nof_words),
+		lpm_widthu_r => ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),
+		lpm_width_r => g_rddat_w,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "ON",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		rdclk => rdclk,
+		wrclk => wrclk,
+		wrreq => wrreq,
+		aclr => aclr,
+		data => data,
+		rdreq => rdreq,
+		wrfull => sub_wire0,
+		q => sub_wire1,
+		rdempty => sub_wire2,
+		wrusedw => sub_wire3,
+		rdusedw => sub_wire4
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "16"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
+-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+-- Retrieval info: USED_PORT: rdusedw 0 0 7 0 OUTPUT NODEFVAL "rdusedw[6..0]"
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
+-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+-- Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+-- Retrieval info: CONNECT: rdusedw 0 0 7 0 @rdusedw 0 0 7 0
+-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_dc_mixed_widths_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf

libraries/technology/altera/altera_mf/altera_mf_fifo_sc.vhd

+-- megafunction wizard: %FIFO%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: scfifo 
+
+-- ============================================================
+-- File Name: altera_mf_fifo_sc.vhd
+-- Megafunction Name(s):
+-- 			scfifo
+--
+-- Simulation Library Files(s):
+-- 			
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
+-- ************************************************************
+
+
+--Copyright (C) 1991-2011 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY common_lib;
+USE common_lib.common_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altera_mf_fifo_sc IS
+  GENERIC (
+    g_use_eab   : STRING := "ON";
+    g_dat_w     : NATURAL;
+    g_nof_words : NATURAL
+  );
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+		rdreq		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		empty		: OUT STD_LOGIC ;
+		full		: OUT STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+		usedw		: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0)
+	);
+END altera_mf_fifo_sc;
+
+
+ARCHITECTURE SYN OF altera_mf_fifo_sc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (usedw'RANGE);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (data'RANGE);
+
+
+
+	COMPONENT scfifo
+	GENERIC (
+		add_ram_output_register		: STRING;
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		underflow_checking		: STRING;
+		use_eab		: STRING
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			usedw	: OUT STD_LOGIC_VECTOR (ceil_log2(g_nof_words)-1 DOWNTO 0);
+			empty	: OUT STD_LOGIC ;
+			full	: OUT STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			aclr	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+			rdreq	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	usedw    <= sub_wire0;
+	empty    <= sub_wire1;
+	full    <= sub_wire2;
+	q    <= sub_wire3;
+
+	scfifo_component : scfifo
+	GENERIC MAP (
+		add_ram_output_register => "ON",
+		intended_device_family => "Stratix IV",
+		lpm_numwords => g_nof_words,
+		lpm_showahead => "OFF",
+		lpm_type => "scfifo",
+		lpm_width => g_dat_w,
+		lpm_widthu => ceil_log2(g_nof_words),
+		overflow_checking => "ON",
+		underflow_checking => "ON",
+		use_eab => g_use_eab
+	)
+	PORT MAP (
+		clock => clock,
+		wrreq => wrreq,
+		aclr => aclr,
+		data => data,
+		rdreq => rdreq,
+		usedw => sub_wire0,
+		empty => sub_wire1,
+		full => sub_wire2,
+		q => sub_wire3
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+-- Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altera_mf_fifo_sc_wave*.jpg FALSE

libraries/technology/fifo/hdllib.cfg

+hdl_lib_name = technology_fifo
+hdl_library_clause_name = technology_fifo_lib
+hdl_lib_uses = technology ip_altera_mf
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    tech_fifo_component_pkg.vhd
+    tech_fifo_sc.vhd
+    tech_fifo_dc.vhd
+    tech_fifo_dc_mixed_widths.vhd
+
+test_bench_files =