Moved or copied common DDIO files from UniBoard to RadioHDL.

libraries/base/common/src/vhdl/common_ddio_in.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Capture double data rate FPGA input
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY common_ddio_in IS
+  GENERIC(
+    g_device_family : STRING := "Stratix IV";
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    in_dat      : IN  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_clk      : IN  STD_LOGIC;
+    in_clk_en   : IN  STD_LOGIC := '1';
+    rst         : IN  STD_LOGIC := '0';
+    out_dat_hi  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat_lo  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+END common_ddio_in;

libraries/base/common/src/vhdl/common_ddio_out.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Double data rate FPGA output or register single data rate FPGA output
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY common_ddio_out IS
+  GENERIC(
+    g_device_family : STRING  := "Stratix IV";
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    rst        : IN   STD_LOGIC := '0';
+    in_clk     : IN   STD_LOGIC;
+    in_clk_en  : IN   STD_LOGIC := '1';
+    in_dat_hi  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_dat_lo  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat    : OUT  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+END common_ddio_out;

libraries/technology/altera/altera_mf/altera_mf_ddio_in.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Capture double data rate FPGA input
+-- Description:
+--   Using the MegaWizard simply provides a GUI to set and select the generics
+--   and IO. First used MegaWizard to learn how this works and what the default
+--   values are:
+--     %UNB%\Firmware\modules\common\src\ip\MegaWizard\ddio_in.vhd
+--   Then directly used the component to define the instance. The component
+--   comes from:
+--     %QUARTUS_ROOTDIR%\..\quartus\eda\sim_lib\altera_mf_components.vhd
+--
+--   component altddio_in
+--     generic (
+--         width                  : positive; -- required parameter
+--         invert_input_clocks    : string := "OFF";
+--         intended_device_family : string := "Stratix";
+--         power_up_high          : string := "OFF";
+--         lpm_hint               : string := "UNUSED";
+--         lpm_type               : string := "altddio_in" );
+--     port (
+--         datain    : in std_logic_vector(width-1 downto 0);
+--         inclock   : in std_logic;
+--         inclocken : in std_logic := '1';
+--         aset      : in std_logic := '0';
+--         aclr      : in std_logic := '0';
+--         sset      : in std_logic := '0';
+--         sclr      : in std_logic := '0';
+--         dataout_h : out std_logic_vector(width-1 downto 0);
+--         dataout_l : out std_logic_vector(width-1 downto 0) );
+--   end component;
+  
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.ALL;
+
+ENTITY altera_mf_ddio_in IS
+  GENERIC(
+    g_device_family : STRING := "Stratix IV";
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    in_dat      : IN  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_clk      : IN  STD_LOGIC;
+    in_clk_en   : IN  STD_LOGIC := '1';
+    rst         : IN  STD_LOGIC := '0';
+    out_dat_hi  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat_lo  : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+END altera_mf_ddio_in;
+
+
+ARCHITECTURE str OF altera_mf_ddio_in IS
+
+BEGIN
+
+  ddio: altddio_in
+  GENERIC MAP (
+    intended_device_family => g_device_family,
+    invert_input_clocks => "OFF",
+    lpm_hint => "UNUSED",
+    lpm_type => "altddio_in",
+    power_up_high => "OFF",
+    width => g_width
+  )
+  PORT MAP (
+    datain      => in_dat,
+    inclock     => in_clk,
+    inclocken   => in_clk_en,
+    aclr        => rst,
+    dataout_h   => out_dat_hi,
+    dataout_l   => out_dat_lo
+  );
+  
+END str;
\ No newline at end of file

libraries/technology/altera/altera_mf/altera_mf_ddio_out.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Double data rate FPGA output or register single data rate FPGA output
+-- Description:
+--   Using the MegaWizard simply provides a GUI to set and select the generics
+--   and IO. First used MegaWizard to learn how this works and what the default
+--   values are:
+--     %UNB%\Firmware\modules\common\src\ip\MegaWizard\ddio_out.vhd
+--   Then directly used the component to define the instance. The component
+--   comes from:
+--     %QUARTUS_ROOTDIR%\..\quartus\eda\sim_lib\altera_mf_components.vhd
+--
+--   component altddio_out
+--       generic (
+--           width                  : positive;  -- required parameter
+--           power_up_high          : string := "OFF";
+--           oe_reg                 : string := "UNUSED";
+--           extend_oe_disable      : string := "UNUSED";
+--           invert_output          : string := "OFF";
+--           intended_device_family : string := "Stratix";
+--           lpm_hint               : string := "UNUSED";
+--           lpm_type               : string := "altddio_out" );
+--       port (
+--           datain_h   : in std_logic_vector(width-1 downto 0);
+--           datain_l   : in std_logic_vector(width-1 downto 0);
+--           outclock   : in std_logic;
+--           outclocken : in std_logic := '1';
+--           aset       : in std_logic := '0';
+--           aclr       : in std_logic := '0';
+--           sset       : in std_logic := '0';
+--           sclr       : in std_logic := '0';
+--           oe         : in std_logic := '1';
+--           dataout    : out std_logic_vector(width-1 downto 0);
+--           oe_out    : out std_logic_vector(width-1 downto 0) );
+--   end component;
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.ALL;
+
+ENTITY altera_mf_ddio_out IS
+  GENERIC(
+    g_device_family : STRING  := "Stratix IV";
+    g_width         : NATURAL := 1
+  );
+  PORT (
+    rst        : IN   STD_LOGIC := '0';
+    in_clk     : IN   STD_LOGIC;
+    in_clk_en  : IN   STD_LOGIC := '1';
+    in_dat_hi  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    in_dat_lo  : IN   STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+    out_dat    : OUT  STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+  );
+END altera_mf_ddio_out;
+
+ARCHITECTURE str OF altera_mf_ddio_out IS
+
+BEGIN
+
+	ddio : ALTDDIO_OUT
+	GENERIC MAP (
+		extend_oe_disable => "OFF",
+		intended_device_family => g_device_family,
+		invert_output => "OFF",
+		lpm_hint => "UNUSED",
+		lpm_type => "altddio_out",
+		oe_reg => "UNREGISTERED",
+		power_up_high => "OFF",
+		width => g_width
+	)
+	PORT MAP (
+		aclr => rst,
+		datain_h => in_dat_hi,
+		datain_l => in_dat_lo,
+		outclock => in_clk,
+		outclocken => in_clk_en,
+		dataout => out_dat
+	);
+  
+END str;
\ No newline at end of file

libraries/technology/altera/altera_mf/hdllib.cfg

@@ -14,5 +14,7 @@ synth_files =
     altera_mf_fifo_dc_mixed_widths.vhd
     altera_mf_fifo_dc.vhd
     altera_mf_fifo_sc.vhd
+    altera_mf_ddio_in.vhd
+    altera_mf_ddio_out.vhd
     
 test_bench_files =